memory BIST


April 16, 2019

Boost your DFT efficiency for AI silicon design

Three hierarchical DFT strategies help cut time-to-market for large AI chips by exploiting regularity and addressing test at the RTL.
Article  |  Topics: Blog Topics, Tested Component to System  |  Tags: , , , , , ,   |  Organizations:
July 7, 2017

How automotive test is evolving for the age of autonomous vehicles

Automotive test has never been easy. Safety made sure of that. But the move to autonomous vehicles is making it more challenging still.
March 9, 2016

IP implementation variety drives latest partnerships

Mentor Graphics' recent deal with ARM illustrates how proliferation in design is influencing deals between tool and IP vendors.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors