Co-design underpins infrastructure acceleration at Google
At the recent VLSI Symposium, Google vice president Parthasarathy Ranganathan described the importance of co-design and the software stack in its data-center designs.
server accelerator
Intel and partners join for RISC-V development push
Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
AMD moves gradually into 3D integration
At December's Design Automation Conference, AMD senior vice president Sam Naffziger provided more insights into the chipmaker’s use of chiplet-based design and manufacture.
Combined database underpins 3DIC design suite
Cadence has built a unified database to support a group of tools to support the planning and implementation of 3DIC designs.
Scaling costs tip balance toward chiplets for AMD server processors
In a panel session at VLSI Symposia, AMD described how the economics have come down strongly in favor of multichip integration for multicore server processors.
ODSA weighs options for chiplet interconnect
An Open Compute Project group working on multichip integration sees a combination of parallel and serial interfaces being important for interchip communication.
Microsoft offers free RTL for fast server compression
Not only has Microsoft decided to make a compression algorithm intended for data centers open source, the company the company is providing its own RTL to anyone who wants to implement it in silicon.