chip-package integration


June 17, 2021

Standard arrives for thermal simulation data

A de facto standard for exchanging thermal information about designs has become JEDEC standard JEP181.
January 19, 2021

Design house recommends earlier start to flip-chip bump layout

Design-services company Sondrel is recommending teams start earlier on package design to avoid delays after IC tapeout.
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June 27, 2018

EDA needs to work on the back end, says Qualcomm

It’s the back-end that needs work as system-level considerations begin to dominate design, Qualcomm’s vice president of engineering said at DAC.
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June 5, 2017

Mentor builds links for multichip package integration

Mentor, a Siemens business, has formed an alliance with foundries and OSAT providers and launched a flow that brings IC and package design together.
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May 30, 2017

Cadence pulls Virtuoso and Allegro closer for 3DIC

Cadence Design Systems has brought its chip- and PCB-design environments closer together as the shift towards multichip packages gains pace.
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May 19, 2017

FinFET-project growth ‘stunning’ says EDA exec

Machine learning, smarter cars, and the infrastructure to support a sixfold increase in IoT and edge devices have helped push up the number of teams doing finFET designs to more than 100, according to Tom Beckley of Cadence.
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June 26, 2015

‘This sensor will self-destruct in the next five (hundred thousand) seconds’

Research by Professor John Rogers' group at the University of Illinois is leading to biodegradable electronics, for both defense and medical applications.
April 24, 2015

Do you need more stress (analysis) in your life?

Mentor Graphics is working on technology to analyse the effects of mechanical stress on integrated circuits, describing progress at the company's U2U conference.
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