A de facto standard for exchanging thermal information about designs has become JEDEC standard JEP181.
Design-services company Sondrel is recommending teams start earlier on package design to avoid delays after IC tapeout.
It’s the back-end that needs work as system-level considerations begin to dominate design, Qualcomm’s vice president of engineering said at DAC.
Mentor, a Siemens business, has formed an alliance with foundries and OSAT providers and launched a flow that brings IC and package design together.
Cadence Design Systems has brought its chip- and PCB-design environments closer together as the shift towards multichip packages gains pace.
Machine learning, smarter cars, and the infrastructure to support a sixfold increase in IoT and edge devices have helped push up the number of teams doing finFET designs to more than 100, according to Tom Beckley of Cadence.
Research by Professor John Rogers' group at the University of Illinois is leading to biodegradable electronics, for both defense and medical applications.
Mentor Graphics is working on technology to analyse the effects of mechanical stress on integrated circuits, describing progress at the company's U2U conference.
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