Originally presented at DVCon Europe, a new paper automates complex steps in RDC verification and reduces noise.
A Japanese component supplier is making it easier for its customers to choose the right parts for their designs by offering a powerful analog and mixed-signal (AMS) simulation environment through its website.
An RF Laboratories engineer provides some tips and techniques in the context of the PADS Professional suite.
A Mentor-Samsung collaboration cuts the need for model-based analysis and speeds analysis runtime by as much as 20X.
Updates to existing designs are often error-prone, though safety tolerances are necessarily tightening. This four-step strategy can help.
A new paper describes a case study for a pressure-sensing IoT application based on the ARM DesignStart platform and Mentor IoT tool flow.
Data-centre networking chip goes through full-chip design rule checking and layout-versus-schematic signoff on TSMC's 16nm finFET process in a day.
Two-year-old design house make IP choice to use Synopsys DesignWare to build an enterprise SSD controller from scratch.
ST has tweaked its standard HLS flow for ISPs to meet the requirements of ISO 26262
Japanese giant uses variable thermal simulation on automotive IC intended for harsh environments.
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