Chipmaker

SureCore and Intrinsic have teamed up to provide a way to implement resistive random-access memory as an SoC-embeddable technology.

From tutorials to technical papers to special 'diamond' sessions, Tessent features large at ITC 2023.

Vertical integration is one of the major focus areas at the upcoming IEDM conference, both in terms of transistors and the multiple channels that will go into them.

DVCon Europe has announced its two keynote presentations, focusing on energy-efficient high-performance computing and machine learning.

Tessolve is bringing its Verification Futures conference to the US with an event scheduled for mid-September.

Backside power delivery could lead to improvements in chip density and more straightforward place-and-route phases according to work presented at this year’s VLSI Symposium.

The Joules RTL Design Studio aims to make coding more aware of aware of physical issues before and after hand-off for implementation.

Western Digital's head of technology set out at the recent VLSI Symposium the ways in which flash makers can scale without costs accelerating.

A UK cryogenic-CMOS research project has taped out its first demonstrator chip for core memory IP expected to be able to operate at close to absolute zero.

Semidynamics has released a customizable vector unit with out-of-order execution support to accompany its 64bit RISC-V processor cores.