The Joules RTL Design Studio aims to make coding more aware of aware of physical issues before and after hand-off for implementation.
Western Digital's head of technology set out at the recent VLSI Symposium the ways in which flash makers can scale without costs accelerating.
A UK cryogenic-CMOS research project has taped out its first demonstrator chip for core memory IP expected to be able to operate at close to absolute zero.
Semidynamics has released a customizable vector unit with out-of-order execution support to accompany its 64bit RISC-V processor cores.
The company says the mixed-signal platform enabled a 5X improvement in verification productivity.
Processor IP company will incorporate custom instructions and other changes in its superscalar core, which includes a novel memory unit for sparse matrices.
Intel Foundry Services has signed a deal with Arm that will see the two companies work on a program of system and design-technology co-optimization.
Nvidia's move into software aimed at mask production and EDA looks to be part of a wider shift to improve yields.
The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circuits.
The Austin-based start-up used Siemens EDA software to deploy a cutting-edge Smart Substrate based on advanced packaging technology.
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