Chipmaker

July 14, 2023

Cadence mixes know-how and AI to bridge RTL gap

The Joules RTL Design Studio aims to make coding more aware of aware of physical issues before and after hand-off for implementation.
Article  |  Topics: Blog Topics, Physical design, RTL, Verification  |  Tags: , , , , ,   |  Organizations: , , ,
July 12, 2023

‘Two wafers are better than one’ for 3D flash

Western Digital's head of technology set out at the recent VLSI Symposium the ways in which flash makers can scale without costs accelerating.
Article  |  Topics: Blog - IP  |  Tags: , , ,   |  Organizations: ,
July 7, 2023

UK consortium tapes out cryo-SRAM

A UK cryogenic-CMOS research project has taped out its first demonstrator chip for core memory IP expected to be able to operate at close to absolute zero.
Article  |  Topics: Blog - IP  |  Tags: , , ,   |  Organizations:
June 1, 2023

Semidynamics adds flexible vectors to RISC-V cores

Semidynamics has released a customizable vector unit with out-of-order execution support to accompany its 64bit RISC-V processor cores.
Article  |  Topics: Blog - IP  |  Tags: , , , , ,   |  Organizations:
April 25, 2023

Alps Alpine composes capacitance IC with Symphony

The company says the mixed-signal platform enabled a 5X improvement in verification productivity.
April 17, 2023

Semidynamics pushes configurability on RISC-V core for HPC

Processor IP company will incorporate custom instructions and other changes in its superscalar core, which includes a novel memory unit for sparse matrices.
Article  |  Topics: Blog - IP  |  Tags: , , ,   |  Organizations: ,
April 13, 2023

Arm signs sub-2nm deal with Intel foundry operation

Intel Foundry Services has signed a deal with Arm that will see the two companies work on a program of system and design-technology co-optimization.
Article  |  Topics: Blog - IP  |  Tags: , , , , , ,   |  Organizations: ,
April 4, 2023

Curvilinear layout looks to wider adoption with mask speedups

Nvidia's move into software aimed at mask production and EDA looks to be part of a wider shift to improve yields.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: , , ,
January 6, 2023

DVCon Europe best paper speeds up memory-controller tests

The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circuits.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations: ,
November 23, 2022

Chipletz pushes packaging design for AI, HPC and immersive use-cases

The Austin-based start-up used Siemens EDA software to deploy a cutting-edge Smart Substrate based on advanced packaging technology.

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