Chipmaker

October 9, 2023

ITC 2023 preview: Siemens DIS

From tutorials to technical papers to special 'diamond' sessions, Tessent features large at ITC 2023.
Article  |  Topics: EDA - DFT  |  Tags:   |  Organizations: , , ,
October 5, 2023

Vertical integration expands at IEDM

Vertical integration is one of the major focus areas at the upcoming IEDM conference, both in terms of transistors and the multiple channels that will go into them.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations: , ,
September 6, 2023

HPC and AI provide keynote focus at DVCon Europe

DVCon Europe has announced its two keynote presentations, focusing on energy-efficient high-performance computing and machine learning.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations: ,
July 25, 2023

Verification Futures heads to the US in September

Tessolve is bringing its Verification Futures conference to the US with an event scheduled for mid-September.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations: , , ,
July 24, 2023

Backside power shows promise but more complex manufacturing

Backside power delivery could lead to improvements in chip density and more straightforward place-and-route phases according to work presented at this year’s VLSI Symposium.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: , ,
July 14, 2023

Cadence mixes know-how and AI to bridge RTL gap

The Joules RTL Design Studio aims to make coding more aware of aware of physical issues before and after hand-off for implementation.
Article  |  Topics: Blog Topics, Physical design, RTL, Verification  |  Tags: , , , , ,   |  Organizations: , , ,
July 12, 2023

‘Two wafers are better than one’ for 3D flash

Western Digital's head of technology set out at the recent VLSI Symposium the ways in which flash makers can scale without costs accelerating.
Article  |  Topics: Blog - IP  |  Tags: , , ,   |  Organizations: ,
July 7, 2023

UK consortium tapes out cryo-SRAM

A UK cryogenic-CMOS research project has taped out its first demonstrator chip for core memory IP expected to be able to operate at close to absolute zero.
Article  |  Topics: Blog - IP  |  Tags: , , ,   |  Organizations:
June 1, 2023

Semidynamics adds flexible vectors to RISC-V cores

Semidynamics has released a customizable vector unit with out-of-order execution support to accompany its 64bit RISC-V processor cores.
Article  |  Topics: Blog - IP  |  Tags: , , , , ,   |  Organizations:
April 25, 2023

Alps Alpine composes capacitance IC with Symphony

The company says the mixed-signal platform enabled a 5X improvement in verification productivity.

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