Cadence has agreed to work with Intel Foundry Services on IP and flows for the 18A process, which will include backside power delivery and nanosheet transistors.
The IEEE Symposium on VLSI Technology & Circuits switches back to Honolulu for its 44th year in the summer of next year and has issued its call for papers, with a deadline of early February for contributions.
Intel Foundry Services has signed a deal with Arm that will see the two companies work on a program of system and design-technology co-optimization.
Adding an MOL layer that takes advantage of a self-aligned pitch-splitting technique and a rotated layout could cut standard-cell height to 4T.
Aiming for a primarily physical event in the fall, organisers of the 2021 IEDM have published the tutorial and short-core schedule.
Imec showed at VLSI Symposia a process flow that can cut the gap between complementary transistors to less than 20nm.
AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.
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