Cadence to work on IP for Intel 18A
Cadence has agreed to work with Intel Foundry Services on IP and flows for the 18A process, which will include backside power delivery and nanosheet transistors.
2nm
VLSI Symposium 2024 looks to bridge digital and physical
The IEEE Symposium on VLSI Technology & Circuits switches back to Honolulu for its 44th year in the summer of next year and has issued its call for papers, with a deadline of early February for contributions.
Arm signs sub-2nm deal with Intel foundry operation
Intel Foundry Services has signed a deal with Arm that will see the two companies work on a program of system and design-technology co-optimization.
Imec adds MOL layer to potentially cut cell size 20%
Adding an MOL layer that takes advantage of a self-aligned pitch-splitting technique and a rotated layout could cut standard-cell height to 4T.
IEDM 2021 publishes course schedule
Aiming for a primarily physical event in the fall, organisers of the 2021 IEDM have published the tutorial and short-core schedule.
Imec cuts transistor gap to less than 20nm with forksheets
Imec showed at VLSI Symposia a process flow that can cut the gap between complementary transistors to less than 20nm.
EDA in the cloud boosts DRC iterations for AMD
AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.