Chipmaker

Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.

Teledyne e2v has demonstrated a prototype optical link that the company believes could replace electrical signaling for remote RF heads.

As the project that funded OpenRoad draws to a close, experts pondered its wider future at the 59th DAC.

Siemens and Nvidia have agreed to work more closely together to drive the development of higher-fidelity digital twins.

R&D multicore processor demonstrates programmable extensions for DSP.

CXL is a strongly-backed technology aimed at improving connectivity across datacenters handling high demand HPC and AI applications.

Intel expects to double logic density through metal scaling and smaller cells with upcoming process.

Imagination Technologies has dropped the requirement to take an upfront licence for some of its IP cores if customers join its Open Access program.

Synopsys and Analog Devices have agreed to provide model libraries for the chipmaker's DC/DC ICs and power regulators that work with the Saber simulation tool.

Chiplets will need models to guarantee heterogenous SiP implementation. A cross-industry working group describes its progress so far.