The Siemens subsidiary is involved with a wide range of tutorials, technical papers and more at this month's San Jose conference.
Codasip has launched the seventh generation of its Studio software for processor design and tuning, aiming to take advantage of the interest in RISC-V as a core instruction set for customized processors.
The RISC-V workshop in California at the end of November 2017 provided the opportunity for Western Digital to commit its own work on processors for internal use to the open-source architecture and for the ecosystem of off-the-shelf cores and tools to expand.
Codasip has added a processor core aimed at low-energy IoT nodes to its growing portfolio of customizable designs based on the RISC-V architecture.
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