Codasip pips Arm to commercial CHERI with RISC-V version
Codasip has put support for a set of instruction extensions intended to secure memory into its RISC-V core designs.
Codasip
RISC-V gets verification and security IP additions
Ahead of the RISC-V Summit in San Jose, Imperas Software has issued updates to its ImperasDV verification IP for RISC-V verification and Codasip has launched a secure-processor initiative.
Intel and partners join for RISC-V development push
Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
‘Shocking’ quality sees vendors organize around RISC-V verification
Three EDA vendors team up to create stronger verification flow for RISC-V processor implementations.
DVCon US 2018 preview: Mentor
The Siemens subsidiary is involved with a wide range of tutorials, technical papers and more at this month's San Jose conference.
Codasip updates processor-architecture tools
Codasip has launched the seventh generation of its Studio software for processor design and tuning, aiming to take advantage of the interest in RISC-V as a core instruction set for customized processors.
Workshop sees the RISC-V ecosystem expand
The RISC-V workshop in California at the end of November 2017 provided the opportunity for Western Digital to commit its own work on processors for internal use to the open-source architecture and for the ecosystem of off-the-shelf cores and tools to expand.
Codasip adds IoT core to RISC-V line
Codasip has added a processor core aimed at low-energy IoT nodes to its growing portfolio of customizable designs based on the RISC-V architecture.
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