Semidynamics pushes configurability on RISC-V core for HPC
Barcelona-based Semidynamics has launched RISC-V processor IP that the company claims provides a great deal more customisability than other off-the-shelf cores on the market and which incorporates a novel memory unit that improves performance on the kinds of sparse data structures used in some machine-learning applications.
The company designed its 64bit RISC-V family of cores for applications that handle large amounts of data in machine learning and high-performance computing (HPC). The cores are process agnostic, with versions being delivered that are intended for use on process geometries down to 5nm.
Though tools such as those from Codasip and Imperas are let designers roll their own RISC-V processors using readymade vanilla cores as templates, Semidynamics is pitching its core as offering high levels of customisability that are not offered by other suppliers.
“Until now, RISC-V processor cores had configurations that were fixed by the vendor or had a very limited number of configurable options such as cache size, address bus size, interfaces and a few other control parameters. Our new IP cores enable the customer to have total control over the configuration, be it new instructions, separate address spaces [or] new memory accessing capabilities,” said Semidynamics CEO and founder, Roger Espasa.
The company said it will incorporate custom instructions into the design if required. “We can implement a customer’s ‘secret sauce’ features into the RTL in a matter of weeks, which is something that no-one else offers,” Espasa claimed.
The first core in the family is the Atrevido, which supports two-way or four-way superscalar operation with out-of-order scheduling, combined with the company’s Gazzillion memory-buffer technology. This unit extends the number of in-flight memory transactions from a typical 8 or 16 to more than 100, allowing more read and write operations to be scheduled by the processor pipeline before stalls occur. The company sees this as important for instructions such as RISC-V’s vector-gather, where there may be as many as 16 different access read requests in one instruction. Recommender AI algorithms often call upon involve sparse data structures where these requests go to different cache lines, with the result being in a standard pipeline that operation cannot continue until of the requests are satisfied. Gazzillion provides more opportunities to schedule around cache misses.
The core has a memory-management unit suitable for Linux-type operating systems and supports both the RISC-V Vector Specification 1.0 as well as the upcoming Semidynamics Open Vector Interface.
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