Semidynamics has released a customizable vector unit with out-of-order execution support to accompany its 64bit RISC-V processor cores.
Processor IP company will incorporate custom instructions and other changes in its superscalar core, which includes a novel memory unit for sparse matrices.
Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
Imperas Software has published an open-source functional-coverage library for RISC-V cores.
R&D multicore processor demonstrates programmable extensions for DSP.
Imperas has put together a suite of tools to verify that custom RISC-V processor cores remain compatible with the common infrastructure behind the open-source instruction set.
This week’s RISC-V Summit in California has seen an expansion to the open-source portfolio being built around the architecture as well as increased support from software vendors such as Wind River.
Arm has relented on its opposition to custom instructions with the decision to let customers add them to V8-M processors.
Andes and SiFive attempt to lower the barriers to entry for SoC designs based on RISC-V processor cores.
Codasip has launched the seventh generation of its Studio software for processor design and tuning, aiming to take advantage of the interest in RISC-V as a core instruction set for customized processors.
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