configurable processors

October 8, 2019

Arm to let customers bolt instructions onto V8 processors

Arm has relented on its opposition to custom instructions with the decision to let customers add them to V8-M processors.
June 18, 2019

RISC-V firms aim for lower-cost design starts

Andes and SiFive attempt to lower the barriers to entry for SoC designs based on RISC-V processor cores.
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January 23, 2018

Codasip updates processor-architecture tools

Codasip has launched the seventh generation of its Studio software for processor design and tuning, aiming to take advantage of the interest in RISC-V as a core instruction set for customized processors.
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December 1, 2017

Workshop sees the RISC-V ecosystem expand

The RISC-V workshop in California at the end of November 2017 provided the opportunity for Western Digital to commit its own work on processors for internal use to the open-source architecture and for the ecosystem of off-the-shelf cores and tools to expand.
June 12, 2016

What’s the shortest time in the universe?

“It’s the time between putting out an open-source ARM core and getting a letter from an ARM lawyer,” says UC Berkeley professor Krste Asanovic. So, some design teams are turning to IP that started out as open source to provide more scope for experimentation.
October 6, 2015

Tensilica vision processor cuts power through memory changes

Memory efficiency has driven the design of the latest video and image processor core developed by Cadence Tensilica.
June 1, 2015

Server, IoT acceleration on Intel’s mind in Altera buy

Altera has agreed to Intel's offer to buy the company, with FPGAs to be integrated into Xeon processors after 2016. Atoms will join programmable logic in IoT-oriented devices.
Article  |  Topics: Blog - Embedded, PCB  |  Tags: , , , , , , ,   |  Organizations: , , ,
January 14, 2015

Cadence updates Xtensa with memory and power saving features

Cadence Design Systems has launched the 11th generation of Tensilica Xtensa customizable processors, with changes for VLIW, power-saving caches and memory accesses.
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May 29, 2014

Synopsys adds vector DSP operations to ARC EM processor IP

Synopsys has developed a digital signal processing (DSP) instruction set extension to its EM family and two cores that employ it.
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November 5, 2013

Synopsys aims at fast real-time apps with ARC HS family

Synopsys has launched the ARC HS family of configurable-processor cores, using superpipelining to target high-performance embedded applications.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , ,   |  Organizations:

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