Imperas builds model of Tenstorrent AI core
Imperas Software has worked with AI specialist Tenstorrent to create and distribute a model of the Ascalon processor core.
configurable processors
Semidynamics adds flexible vectors to RISC-V cores
Semidynamics has released a customizable vector unit with out-of-order execution support to accompany its 64bit RISC-V processor cores.
Semidynamics pushes configurability on RISC-V core for HPC
Processor IP company will incorporate custom instructions and other changes in its superscalar core, which includes a novel memory unit for sparse matrices.
Imperas and Synopsys team on RISC-V debug
Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
Imperas releases RISC-V coverage library as open source
Imperas Software has published an open-source functional-coverage library for RISC-V cores.
SoC project uses eFPGA to extend DSP instructions
R&D multicore processor demonstrates programmable extensions for DSP.
Imperas pulls together tools for RISC-V verification
Imperas has put together a suite of tools to verify that custom RISC-V processor cores remain compatible with the common infrastructure behind the open-source instruction set.
Support for RISC-V expands at summit
This week’s RISC-V Summit in California has seen an expansion to the open-source portfolio being built around the architecture as well as increased support from software vendors such as Wind River.
Arm to let customers bolt instructions onto V8 processors
Arm has relented on its opposition to custom instructions with the decision to let customers add them to V8-M processors.
RISC-V firms aim for lower-cost design starts
Andes and SiFive attempt to lower the barriers to entry for SoC designs based on RISC-V processor cores.