HPC and AI provide keynote focus at DVCon Europe
DVCon Europe has announced its two keynote presentations, focusing on energy-efficient high-performance computing and machine learning.
Chipmaker
Verification Futures heads to the US in September
Tessolve is bringing its Verification Futures conference to the US with an event scheduled for mid-September.
Backside power shows promise but more complex manufacturing
Backside power delivery could lead to improvements in chip density and more straightforward place-and-route phases according to work presented at this year’s VLSI Symposium.
Cadence mixes know-how and AI to bridge RTL gap
The Joules RTL Design Studio aims to make coding more aware of aware of physical issues before and after hand-off for implementation.
‘Two wafers are better than one’ for 3D flash
Western Digital's head of technology set out at the recent VLSI Symposium the ways in which flash makers can scale without costs accelerating.
UK consortium tapes out cryo-SRAM
A UK cryogenic-CMOS research project has taped out its first demonstrator chip for core memory IP expected to be able to operate at close to absolute zero.
Semidynamics adds flexible vectors to RISC-V cores
Semidynamics has released a customizable vector unit with out-of-order execution support to accompany its 64bit RISC-V processor cores.
Alps Alpine composes capacitance IC with Symphony
The company says the mixed-signal platform enabled a 5X improvement in verification productivity.
Semidynamics pushes configurability on RISC-V core for HPC
Processor IP company will incorporate custom instructions and other changes in its superscalar core, which includes a novel memory unit for sparse matrices.
Arm signs sub-2nm deal with Intel foundry operation
Intel Foundry Services has signed a deal with Arm that will see the two companies work on a program of system and design-technology co-optimization.
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