Chipmaker

At December's Design Automation Conference, AMD senior vice president Sam Naffziger provided more insights into the chipmaker’s use of chiplet-based design and manufacture.

FHE use-cases are evolving and the NextFlex consortium is looking to smooth their path with a strategy, PDKs and reference modules.

Breker will highlight its latest work on stress-testing processor, storage and I/O architectures during DAC 2021 this week.

DAC 2021 is looming and here is our first round up of a major EDA player's plans for the physical event in San Francisco.

A £6.5m grant will fund the development of memories and other IP to improve the control of qubits in quantum computers.

Emulation capacity and its scalability is a major issue for large SoC designs, said panelists at DVCon Europe.

In a panel at this week’s DVCon Europe, experts described a number of issues facing teams looking to incorporate machine learning in logic verification flows and why some of those efforts will not pay off while others succeed.

Arm’s SystemReady program has revealed a number of the subtleties involved when trying to maintain software compatibility with operating systems without moving to the straightjacket of platforms like those used for the x86-based PC.

Arm has used machine-learning tools supplied by the Solido group at Siemens Digital Industries Software to speed up IP validation runtime a thousand-fold compared to conventional statistical methods.

Three highlighted papers at IEDM, taking place in December, show the different approaches to the use of the vertical dimension to cut energy use and improve density.