interposer

November 20, 2023

ETRI builds flow for AI chiplets

South Korea's leading research institute has built a reusable flow for lower power petaflops-performance AI.
Article  |  Topics: Blog - EDA, - HPC, Next Generation Design, Packaging, Verification  |  Tags: , , ,   |  Organizations: , ,
November 23, 2022

Chipletz pushes packaging design for AI, HPC and immersive use-cases

The Austin-based start-up used Siemens EDA software to deploy a cutting-edge Smart Substrate based on advanced packaging technology.
September 27, 2022

Siemens automates test to handle multi-die 2.5D, 3D and 5.5D architectures

Tessent Multi-die extends the capabilities of the DFT suite in line with new standards intended to enable widespread adoption of interposer and stacked die strategies.
Article  |  Topics: EDA - DFT  |  Tags: , , , , , , , , , ,   |  Organizations:
February 10, 2022

Capturing connectivity for assembly verification in 2.5D and 3D design

Learn how to ingest data from multiple engineering teams in multiple formats on interposer and other multi-dimensional projects.
Article  |  Topics: Verification  |  Tags: , , , , , , , , ,   |  Organizations:
February 8, 2022

How digital twin evaluations optimize STCO-based design

System Technology Co-optimization raises various SI, PI, thermal, mechanical and warp risks due to its use of advanced packaging. Early-stage prototyping mitigates them.
January 25, 2022

Choose the right advanced packaging methodology for metal fill rules

Advanced packaging requirements from foundries and OSATs pose stringent challenges. A new paper describes three ways of satisfying them.
July 8, 2020

Scaling costs tip balance toward chiplets for AMD server processors

In a panel session at VLSI Symposia, AMD described how the economics have come down strongly in favor of multichip integration for multicore server processors.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations:
April 5, 2018

Leti releases photonics design kit for Synopsys PhoeniX OptoDesigner suite

PDK enables photonics prototyping on MPW runs and compatibility with volume production at STMicroelectronics at Crolles.
Article  |  Topics: Blog - EDA, IP, - Product  |  Tags: , ,   |  Organizations: , ,
March 27, 2014

Intel and Altera extend foundry deal into interposer and full 3D

Deal quashes rumors that Altera was about to move its cutting edge production back to TSMC, but nor does it appear to be 'exclusive' for 3D products.
Article  |  Topics: Design to Silicon, Blog - EDA  |  Tags: , , , , ,   |  Organizations: , ,
November 7, 2013

TSMC demonstrates readiness for 3D-IC

Research projects to verify methodologies, address third-party integration challenges and add a low-cost interposer-like technology to the 3D-IC family make their mark.
Article  |  Topics: Commentary, Conferences, Design to Silicon  |  Tags: , , , , ,   |  Organizations: ,

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