Aim for power first for best place-and-route results

Janet Attar is Product Marketing Manager at Siemens EDA responsible for Aprisa, Siemens’ place and route solution. She has over 15 years of experience in the semiconductor industry. Prior to Siemens, Janet was an Applications Engineer for Cadence Design Systems and a Physical Design Engineer for International Rectifier (now Infineon Technologies).

Among the key targets in place-and-route—performance, power, and area (PPA) — performance has traditionally been the primary focus. Low power has been gaining in importance though, particularly at today’s advanced process nodes. No one wants lower-performing chips, so place-and-route tools employ a variety of strategies to achieve the lowest power without sacrificing performance.

Place-and-route software is not all the same. Physical design tools with older software architectures can lead to delays in time-to-closure and sub-optimal results because they use multiple different data models. A design tool built on a single-unified data model and using modern algorithms is intended to be faster, easier to use, and capable of producing the best PPA for today’s hierarchical and block-level designs.

Place-and-route software can help designers address the many challenges of low-power designs depending on a couple of factors:

• How well the software handles multiple power domains; and
• The kind of optimizations the software performs throughout the flow.

Managing multiple power domains

Multi-power domain support ensures all the elements required in a low power design are included and used in accordance with the low-power specs. The software used in the digital implementation flow must be able to buffer on multiple power domains without errors and perform placement of all power management cells such as level shifters, isolation cells, power switch cells, and retention flip-flops. Power-sensitive designs also require the routing of secondary power/ground pins and routing to the power grid inside the voltage islands.

Look for place-and-route software that offers comprehensive multi-power domain support and supports the Unified Power Format (UPF). It should automatically insert power management cells, such as isolation cells, level shifters, power switches, always-on/regular buffer selection, and so on. It is very useful to have a built-in power domain checker to flag any errors related to power domain, cell placement, connectivity, and buffering without the need for an external tool.

Optimizing designs for low power

With the design goal of meeting strict power specifications without sacrificing performance, the place-and-route tool should use low power as the top priority and work towards that goal throughout the flow. You can do this by using techniques like activity-driven placement and routing for lower dynamic power (Figure 1). By starting with the power metric as the top goal during optimization, the place-and-route flow can achieve the best possible power for that node, library, and design specs, and then optimize from that point to reach the timing target. This method is more effective than trying to recover power once the most power-hungry cells have already been used in the design to achieve timing.

Figure 1. Managing coupling capacitance at various steps with activity-driven optimizations (Siemens EDA – click to enlarge)

Techniques deployed in a ‘power first’ methodology include:

• Clock transition fixing for better power;
• Tradeoff small timing for large power reduction in CTS;
• Multi-bit-register merging and de-merging; and
• Full LVF analysis and optimization to reduce over-design.

Results from a commercial place-and-route tool’s PowerFirst methodology

The Siemens’ Aprisa place-and-route software uses PowerFirst optimization to reduce the internal, switching, and leakage power of the most power-sensitive designs while minimizing timing tradeoffs. In an industrial design, a DDR PHY in 7 m with about 1.3M instances and a 1 GHz frequency, PowerFirst techniques reduced the total power by 16% compared to Aprisa in timing-only mode while maintaining the achieved timing correlated to signoff. Aprisa’s results also beat the incumbent place-and-route solution (Figure 2).

Figure 2. Results of Aprisa PowerFirst on internal, switching, and leakage power at sign-off (Siemens EDA – click to enlarge)

Built-in power domain checker

When targeting low power during place-and-route, design teams can save time and frustration by using a built-in power domain checker to verify the multi-voltage setup, power management cells, and correct connectivity (Figure 3). A power domain checker can identify all the power domain-related errors without the need of an external verification tool and long before going to signoff. This can ensure correct-by-design low-power methodology and that power management cells are used as required.

Figure 3. Built-in Power Domain Checker (Siemens EDA – click to enlarge)

It is possible to achieve lower power usage during place-and-route by using software designed to do so with the following features:

• Full support for all industry-standard power formats and for multiple power domains, including offering a built-in power domain checker;
• A unified data model which is shared throughout the entire flow that allows real routing information and parasitics to be available to each step in the flow, resulting in consistent timing and DRC and excellent correlation to signoff tools.

You can learn more about the low-power place-and-route software from Siemens in this technical paper.