A flexible and still evolving range of 5G standards requires methodologies that can handle massive test.
CEVA has reworked its XC architecture to provide what the company claims is the kind of performance boost needed to handle phase-two 5G applications once Release 17 rolls out.
A SystemC/C++ app from a library that extends the OneSpin 360 DV-Verify platform was used by ML IP specialist NanoSemi on a 5G/WiFi project.
Achronix has incorporated direct support for machine learning into the latest version of its eFPGA architecture.
Mentor's updated AMS platform claims performance boost by obviating 'legacy' technology.
Mentor has added three companies since its acquisition a little over a year ago - and there's method to this buying spree.
The embedded FPGA is beginning to find a market, with communications leading the way but machine learning likely to drive further adoption.
It’s the back-end that needs work as system-level considerations begin to dominate design, Qualcomm’s vice president of engineering said at DAC.
Strato emulator family adds modular boxes that can build from 640K and 1.25B gate-counts for automotive, mil/aero markets and 'digital twin' strategies.
Ceva has decided to include neural network, vector processing and customized instruction sets in an IP platform for 5G NR terminals.
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