Equivalence checking supports the efficient reuse of designs that reside on out-of-date silicon but remain valid in their own right.
Functional verification for increasingly complex ARM-based designs is at the heart of the new consultancy partnership.
A new technical article discusses Renesas' addition of SLEC to its SystemC and RTL flows and the improvements it achieved in time and coverage..
The third part of this series takes the original CNN demonstrator through a full ISO 26262 type functional safety workflow
An object classification demonstrator shows how high-level synthesis (HLS) can speed the delivery and exploration of automotive design.
Not only has Microsoft decided to make a compression algorithm intended for data centers open source, the company the company is providing its own RTL to anyone who wants to implement it in silicon.
Closing code coverage from HLS has been tricky because the C++ tools were built for software not hardware. But that is changing.
ST has tweaked its standard HLS flow for ISPs to meet the requirements of ISO 26262
SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.
Cutting the cabling to simplify the emulation process.
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