RTL

September 8, 2022

Use equivalence checking to retarget obsolete FPGA designs

Equivalence checking supports the efficient reuse of designs that reside on out-of-date silicon but remain valid in their own right.
October 22, 2020

Mentor and Arm collaborate on RTL verification reviews

Functional verification for increasingly complex ARM-based designs is at the heart of the new consultancy partnership.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , ,   |  Organizations: ,
February 28, 2020

Learn how Renesas uses SLEC to enhance its verification flows

A new technical article discusses Renesas' addition of SLEC to its SystemC and RTL flows and the improvements it achieved in time and coverage..
Article  |  Topics: Blog - EDA, - HLS  |  Tags: , , ,   |  Organizations: ,
October 4, 2019

Master the design and verification of next gen transport: Part Three – functional safety

The third part of this series takes the original CNN demonstrator through a full ISO 26262 type functional safety workflow
October 2, 2019

Master the design and verification of next gen transport: Part Two – high-level synthesis

An object classification demonstrator shows how high-level synthesis (HLS) can speed the delivery and exploration of automotive design.
March 20, 2019

Microsoft offers free RTL for fast server compression

Not only has Microsoft decided to make a compression algorithm intended for data centers open source, the company the company is providing its own RTL to anyone who wants to implement it in silicon.
Article  |  Topics: Blog - IP  |  Tags: , , , , ,   |  Organizations: ,
December 31, 2018

Closing code coverage with a hardware-aware HLS-to-RTL flow

Closing code coverage from HLS has been tricky because the C++ tools were built for software not hardware. But that is changing.
Article  |  Topics: Blog Topics  |  Tags: , , , , ,   |  Organizations:
December 7, 2017

Discover how ST adapted HLS for automotive imaging

ST has tweaked its standard HLS flow for ISPs to meet the requirements of ISO 26262
June 18, 2013

Real Intent highlights hierarchical clock domain crossing with Meridian 5.0

SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.
Article  |  Topics: Blog - EDA, - RTL, Verification  |  Tags: , ,   |  Organizations: ,
April 25, 2012

No more spaghetti

Cutting the cabling to simplify the emulation process.
Article  |  Topics: Commentary, Design to Silicon, Blog - EDA, - Industry Blogs  |  Tags: ,   |  Organizations:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors