Xilinx plans to add high-speed analog interfaces to its upcoming field-programmable gate arrays (FPGAs) to better support high-density 5G basestation designs.
The decision follows an extensive R&D project that include a system-in-package (SIP) approach based on time-multiplexed data converters featured at the International Solid State Circuits Conference (ISSCC) in 2014. The company plans to take advantage of finFET performance so that the final products can be fully monolithic.
Kirk Saban, senior director of FPGA and SoC product management at Xilinx, said the company has fabbed 16nm test chips at foundry TSMC that incorporate the analog-to-digital and digital-to-analog converter circuitry. “And we will take this technology to market on 16nm. It will be an extension of the MPSoC UltraScale family.”
Aiming at basestations that make extensive use of multiple-input, multiple-output (MIMO) RF techniques, Xilinx’ idea is to use gigahertz-rate ADCs and DACs to perform direct downconversion from RF to digital. That will make it possible to remove an array of offchip ADCs and analog front-end components such as mixers used in conventional basestation architectures.
“Looking at what’s happening in the 5G marketplace, there is going to be a proliferation of MIMO-class radios. The tier-one suppliers are looking to reduce the footprint and the BoM complexity of their designs, from macrocells down to picocells,” Saban noted. “This technology is also ideal for wireless backhaul.”
Saban claimed the integration would not only reduce overall circuit-board complexity but power consumption as well, partly because the integrated ADCs and DACs remove the need to support offchip JESD204 serial links between the FPGAs and converters. The company also expects, by being based on a finFET process, its integrated approach will demonstrate higher energy efficiency than discrete analog front-ends fabbed on older technologies. This, in turn, should allow complex electronics to be moved closer to the antenna arrays themselves.
“We see a move towards remote radio units. Previously, the radio units were deployed separate from the antenna array. Now we are seeing a move towards active antenna arrays, where the electronics package is integrated with the antenna,” Saban claimed. “But this makes the thermal environment more difficult: it can no longer be an actively cooled system. That is driving the need to radically reduce power consumption.
“There is a hugh push to get to 8×8 MIMO but everyone is struggling with power and board space. We expect to see our technology broadly adopted in 4×4 and 8×8 designs,” he added. “Beyond that, 64×64 is becoming popular. That is not something you can do with single-chip implementations but with this architecture we can reduce its footprint considerably.”
The company expects its 12bit ADC to run at up 4Gsample/s and the 14bit DAC at 6.4GS/s. The FPGAs will include DSP blocks tuned for digital mixing and filtering. The multichip architecture developed in 2014 used time multiplexing across multiple ADCs to reach gigahertz performance. On the finFET technology, the core converter speeds are significantly higher so that only two basic blocks are needed to reach the peak sampling rates.
“We have the ability to break them in half into two 2Gsample/s ADCs,” Saban said. “We can support either mode of operation.”
The converters will be deployed in blocks. “There will be quads of 4Gsample/s ADCs, as well as DACs, and there will be multiple quads on a device depending on the product family,” Saban claimed.
“This won’t be a one-size-fits-all solution. There will be radio deployments in all sorts of places. That is driving modularity of design. With our architecture, you will be able to scale your IP across a broad range of designs. You can put in chips to support 2×2, 4×4, 8×8 and so on: it’s just a matter of scaling up. It gives manufacturers a common platform that they can leverage up and down the portfolio.”
Although isolation between the digital and analog sections of the FPGA and the overall circuit board itself could be problematic, Saban noted, “There are some unique things at our disposal. If you look at the sizes of the chips we build, we have a lot more power and ground pins at our disposal than competitors making discrete converters do. We get better isolation by taking advantage of the fact that the ball-grid packages we use are well north of a thousand pins. We have a lot more resources at the package-substrate level and at the CMOS level at our disposal to get the isolation we need than others.
“We’ve also gained a lot of experience in integrated serdes transceivers. That experience has been very applicable to these new devices in terms of isolation,” Saban added.