Learn how to simplify power states in UPF

By TDF Staff |  No Comments  |  Posted: December 6, 2017
Topics/Categories: Blog - EDA, - Standards, Verification  |  Tags: , , ,  | Organizations: , , ,

The latest edition of the Unified Power Format (UPF – IEEE 1801) low-power verification methodology addresses a recently growing concern with the definition of power states. Mentor, a Siemens business, has just released a white paper originally presented at DVCon 2017 that describes the advantages of the new mechanism.

The revisions address problems with UPF’s original power state table (PST) construct. This worked well enough when UPF was first introduced, a little over a decade ago. But defining the tables has become increasingly tedious as low-power design has evolved.

Today, designs can have many more power states than before. Moreover, the ‘shift left’ paradigm has seen power-aware verification move earlier in the design flow: rigidly defining a power state early in a still evolving project, and then potentially having to rework the PST again and again has obvious drawbacks.

To that end, UPF is phasing out the tables and introducing three new semantics within the ‘add_power_state’ command: “deferred”, “indefinite” and “definite”. As their names suggest, these allow the low-power elements of a design to be refined and also an early start to verification. Similarly, they provide greater flexibility in terms of design and IP integration at different levels of abstraction.

The Mentor white paper – ‘Free Yourself from the Tyranny of Power States Tables with Incrementally Refinable UPF‘ – takes a very detailed look at the possibilities offered by the new command. It features detailed design and coding examples, as well as case studies for fundamental power states.

The paper argues that while the replacement of PSTs with ‘add_power_state’ is conceptually “straightforward and simple”, the change itself will “impact the power specification methodologies, power aware verification algorithms, tools, techniques and the entire design, verification and implementation flow”.

The paper is available for immediate download from the link above.

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