Tessent test suite targets automotive, AI and IoT projects that need embedded non-volatile memory.
Embedded magnetic RAM is emerging as a contender for on-chip memory not just from a density standpoint but from that of power.
GlobalFoundries has decided to put development of its 7nm process on the backburner and focus on its existing finFET and FD-SOI processes.
Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.
Movellus has launched the first of a series of IP-creation tools with one that will build all-digital PLLs and integrate them into a design.
Synopsys video details challenges of 10nm design and its collaboration with Samsung Semiconductor to build a full flow to address them.
Altera is using a combination of Intel's 14nm process technology and multidie packaging to boost the logic-cell count for its FPGAs, together with a superpipelining strategy to help balance area and clock speed.
Panel discusses Moore's law scaling beyond the 14nm node to 5nm, where economic, device, interconnect, materials, lithography and design issues abound
Samsung, Synopsys and ARM have been working together to create a finFET design ecosystem.
The 2013 edition of the International Technology Roadmap for Semiconductors has been published. The latest set of tables underlines the slowdown in some aspects of scaling, particularly when it comes to metal interconnect.
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