14nm

December 16, 2019

Mentor delivers eMRAM test for ARM/Samsung FDSOI at 28nm

Tessent test suite targets automotive, AI and IoT projects that need embedded non-volatile memory.
December 12, 2018

IEDM shows progress on embedded eMRAM

Embedded magnetic RAM is emerging as a contender for on-chip memory not just from a density standpoint but from that of power.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations: , , ,
August 28, 2018

GlobalFoundries stops 7nm work to focus on existing processes

GlobalFoundries has decided to put development of its 7nm process on the backburner and focus on its existing finFET and FD-SOI processes.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , , ,   |  Organizations:
June 25, 2018

Node-variant FinFET tweaks try to improve cost, performance

Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations: , ,
January 31, 2018

Analog blocks go digital for faster integration

Movellus has launched the first of a series of IP-creation tools with one that will build all-digital PLLs and integrate them into a design.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:
August 27, 2016

Creating a reference design flow for 10nm processes: video

Synopsys video details challenges of 10nm design and its collaboration with Samsung Semiconductor to build a full flow to address them.
Article  |  Topics: Conferences, Design to Silicon, Blog - EDA  |  Tags: , ,   |  Organizations: ,
June 8, 2015

Altera boosts density and pipelining in finFET FPGA shift

Altera is using a combination of Intel's 14nm process technology and multidie packaging to boost the logic-cell count for its FPGAs, together with a superpipelining strategy to help balance area and clock speed.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , ,   |  Organizations:
June 13, 2014

Path to 5nm plotted at DAC panel

Panel discusses Moore's law scaling beyond the 14nm node to 5nm, where economic, device, interconnect, materials, lithography and design issues abound
Article  |  Topics: Conferences, Blog - EDA  |  Tags: , , , , , ,   |  Organizations: , , ,
June 2, 2014

Samsung certifies Synopsys tools, IP at 14nm

Samsung, Synopsys and ARM have been working together to create a finFET design ecosystem.
Article  |  Topics: Conferences, Design to Silicon, Blog - IP  |  Tags: ,   |  Organizations: , ,
April 7, 2014

Latest ITRS underlines slowdown in interconnect and IC scaling

The 2013 edition of the International Technology Roadmap for Semiconductors has been published. The latest set of tables underlines the slowdown in some aspects of scaling, particularly when it comes to metal interconnect.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: , ,

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