Sonics adds heat-aware DVFS to SoC power controller

By Chris Edwards |  No Comments  |  Posted: June 27, 2017
Topics/Categories: Blog - EDA, IP  |  Tags: , , , , ,  | Organizations: ,

Sonics has developed a version of its power-management IP core for SoCs that adds support for dynamic voltage and frequency scaling (DVFS), along with the ability to tune settings according to temperature.

The ICE-P3 follows a year after the introduction of what the company’s calls an “energy-processing unit”. The architecture used in the original ICE-G1 split the SoC into a collection of power-island “grains”, each with its own monitor and state machine that reacts to triggering events. The ICE-G3 introduced an overarching cluster controller that helps manage the sequencing of power transitions among the different grains. It can ensure that grains turn on and off in the right order and helps the hardware schedule power-state transitions without having to invoke software routines on one of the SoC’s microprocessor cores.

“You may have to turn one grain on first because it contains memory that one of the other grains is dependent on,” explained Sonics founder and CTO Drew Wingard. “With ICE-P3, we added the ability to set one or more performance indices: pointers to a table of voltage and frequency scaling settings.

“The reason we do the extra level of indirection is because the table can include entries based on the current temperature. It’s for people doing more aggressive frequency and voltage control. ‘What’s the minimum supply voltage that allows me to run at 700MHz?’ That depends on the current temperature. Our hardware walks the table to find out the right values,” Wingard added.

Table entries can be extended to include parameters such as bias voltage to suit implementation on silicon-on-insulator (SOI) processes, such as GlobalFoundries’ FDX, that support back-bias leakage and performance control.

One tradeoff in DVFS-based designs is the granularity of control. Additional power regulators tend to push average energy consumption up because each of them will leak power and remove the benefit of being able to tune the voltage supplied to each part of the SoC. The ICE-P3 includes support for arbitration between grains to set a minimum voltage that is suitable for all of the active cores that share the same rail. “We combine modal power with DVFS in ways people haven’t done before,” Wingard said.

“We break energy control into three steps. The first is identification: is it a good time to change? Then there is the actual sequencing and then the detailed control. The detailed control circuits are simple. Even sequencing is reasonably simple. The more difficult part is the identification but I think we have a good isolation of those concerns,” Wingard said.

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