Ceva's latest iteration of its XC architecture aims at the intensive DSP required for 5G basestations.
Xilinx plans to add high-speed analog interfaces to its upcoming FPGAs to better support high-density 5G basestation designs.
S3 Group has launched the second in a family of low-power successive-approximation ADCs, with a design that supports sample rates up to 320MS/s.
Nokia Siemens Networks has built an instrument able to handle bandwidths up 1GHz to investigate the use of milllimeter-band radio for 5G communications.
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