high level synthesis (HLS)

June 27, 2019

Building an ecosystem around HLS for AI and ML designs

Mentor's AI Accelerator Ecosystem adds reference designs, libraries and other forms of support around its Catapult HLS platform.
June 4, 2019

Two-year surge is no blip – Wally Rhines

Wally Rhines, CEO Emeritus of Mentor, a Siemens business, delivered a bullish prognosis for the semiconductor and EDA sectors in a talk at the beginning of the Design Automation Conference in Las Vegas this week.
May 23, 2019

AI and ML fuel Catapult and Calibre updates

Mentor takes the wraps off new machine learning fueled features in its HLS and physical design families ahead of DAC 2019.
February 15, 2019

China Focus 1: Wally Rhines maps startup and design growth

In the first of a weekly series on China's evolving design sector, we look at how the Mentor President and CEO identifies some of the key drivers.
December 31, 2018

Closing code coverage with a hardware-aware HLS-to-RTL flow

Closing code coverage from HLS has been tricky because the C++ tools were built for software not hardware. But that is changing.
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July 30, 2018

HLS speeds up IP deployment at FotoNation

IP supplier FotoNation has decided to embrace the use of high-level synthesis in the creation of cores for smartphones and other high-integration, low-power systems.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , ,   |  Organizations:
May 11, 2015

Altera uses hierarchical approach to speed up FPGA compiles

Altera is revamping the Quartus II software for its FPGAs with a mapping and synthesis engine aimed at the upcoming Gen 10 products, as well as adding a C/C++ front-end for system-level design.
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February 25, 2015

Real Intent updates linter for aviation, Mathworks and SystemVerilog

Ascent Lint adds checks for DO-254, tighter integration with HDL Coder, more SystemVerilog support and new VHDL and Verilog rules in March update.
February 25, 2015

Cadence combines HLS tools in Stratus release

Cadence Design Systems has tied together the Forte Synthesiser and the internally developed C-to-Silicon tools into a new high-level synthesis (HLS) environment the company has titled Stratus.
Article  |  Topics: Blog - EDA, IP  |  Tags: ,   |  Organizations:
January 5, 2015

Cadence high-level synthesis changes deal with congestion

SystemC coding style can lead to excessive congestion in the logic generated by high-level synthesis. Cadence described how it is attacking the issue at its recent Front-End Design Summit.

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