In the first of a weekly series on China's evolving design sector, we look at how the Mentor President and CEO identifies some of the key drivers.
Closing code coverage from HLS has been tricky because the C++ tools were built for software not hardware. But that is changing.
IP supplier FotoNation has decided to embrace the use of high-level synthesis in the creation of cores for smartphones and other high-integration, low-power systems.
Altera is revamping the Quartus II software for its FPGAs with a mapping and synthesis engine aimed at the upcoming Gen 10 products, as well as adding a C/C++ front-end for system-level design.
Ascent Lint adds checks for DO-254, tighter integration with HDL Coder, more SystemVerilog support and new VHDL and Verilog rules in March update.
Cadence Design Systems has tied together the Forte Synthesiser and the internally developed C-to-Silicon tools into a new high-level synthesis (HLS) environment the company has titled Stratus.
SystemC coding style can lead to excessive congestion in the logic generated by high-level synthesis. Cadence described how it is attacking the issue at its recent Front-End Design Summit.
More lint rules, better SystemVerilog support, links to MATLAB and Simulink
EDA giant cites high-level synthesis' move into the mainstream as driven by IP integration challenges in striking deal for the HLS market leader.
Calypto has combined the Catapult high-level synthesis (HLS) tool with elements of its PowerPro software to focus on the demand for lower-power SoC designs.
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