Catch up with the state-of-the-art in ‘shift left’
Just how much of the flow has already has 'shift left' benefit and what is fueling further progress.
ESL/SystemC
DAC 2021 Preview: Siemens EDA
DAC 2021 is looming and here is our first round up of a major EDA player's plans for the physical event in San Francisco.
Coronavirus Resources: Mentor
Live and on-demand videos as well as You Tube 'tips and techniques' clips form part of a wide 'work at home' support package from Mentor.
Master the design and verification of next gen transport: Part Two – high-level synthesis
An object classification demonstrator shows how high-level synthesis (HLS) can speed the delivery and exploration of automotive design.
EDA with ‘AI inside’ – Mentor’s Joe Sawicki offers an insider’s view
Mentor has a host of tools - some public, some not - that leverage AI and ML. EVP Joe Sawicki has been describing the strategy behind their development.
Making the case for HLS in autonomous drive
The automotive market faces challenges that make it a prime candidate for the greater use of high-level synthesis on designs with AI and ML content.
China Focus 1: Wally Rhines maps startup and design growth
In the first of a weekly series on China's evolving design sector, we look at how the Mentor President and CEO identifies some of the key drivers.
Arm TechCon 2017 preview: Mentor
Mentor will present seven papers during the ARMTech Con and a dedicated session, and exhibit at Booth #606.
Wally Rhines looks beyond ‘endless verification’ to the system era
DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.
Virtual prototyping case study focuses on address mapping, clocking and QoS in DDR memory interface optimisation
Case study applies virtual prototyping to optimise address mapping, clock frequency, and Quality of Service configurations to meet DDR performance goals.
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