Konica Minolta describes how it has constructed a C++ signoff flow that mitigates code ambiguity, manual analysis and other inefficiencies.
A SystemC/C++ app from a library that extends the OneSpin 360 DV-Verify platform was used by ML IP specialist NanoSemi on a 5G/WiFi project.
Mentor's AI Accelerator Ecosystem adds reference designs, libraries and other forms of support around its Catapult HLS platform.
Mentor takes the wraps off new machine learning fueled features in its HLS and physical design families ahead of DAC 2019.
Menta eFPGA IP is highly configurable making it well suited to the evolving designs that exploit HLS abstraction.
Closing code coverage from HLS has been tricky because the C++ tools were built for software not hardware. But that is changing.
ST has tweaked its standard HLS flow for ISPs to meet the requirements of ISO 26262
Mentor will present seven papers during the ARMTech Con and a dedicated session, and exhibit at Booth #606.
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