low-power design

June 9, 2016

2D tools adapt to create smaller monolithic 3DIC designs

Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.
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May 25, 2016

DAC 2016 preview: Mentor Graphics

An overview of the vendor's busy DAC program from panels to technical sessions to a one-to-one with Wally Rhines.
June 23, 2015

Sonics updates tune memory and link width for speed and power

The latest release of the SonicsGN NoC infrastructure provides speedups for multichannel memories.
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June 11, 2015

Two-day app challenge results in RTL power analyzer

For DAC 2015, Invionics set itself the challenge of developing a custom tool in 48 hours based on votes for ideas provided by visitors to the show.
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June 8, 2015

CEA-Leti adds partners to FD-SOI low-power design centre

Silicon Impulse program adds partners to ease industrialisation of ultra-low power IC designs based on FD-SOI processes
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June 8, 2015

Synopsys to acquire Atrenta

Atrenta's SpyGlass line and others to be absorbed in Verification Continuum and Galaxy as part of EDA's latest major consolidation.
June 7, 2015

Docea adds API to model power software interactions

Docea Power has added a programming interface to the latest version of its Aceplorer power-modeling software to show how chipset designs would fare under a variety of software-based power-management algorithms.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations:
June 3, 2015

Cadence deploys parallel strategy for faster synthesis

RTL synthesis has joined the array of tools developed by Cadence Design Systems that employ distributed processing, with the aim of exploring more ways of creating area- and power-efficient logic blocks.
May 27, 2015

Mentor zooms in on power peaks with emulator interface

Mentor Graphics has released a programming interface to its Veloce emulators intended to support faster and more accurate power estimation.
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May 18, 2015

Sonics readies fine-grained power-gating architecture

Sonics is moving into power management with an approach intended to substantially automate much of the job of building finely grained power-gated SoCs.
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