low-power design

Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.

An overview of the vendor's busy DAC program from panels to technical sessions to a one-to-one with Wally Rhines.

The latest release of the SonicsGN NoC infrastructure provides speedups for multichannel memories.

For DAC 2015, Invionics set itself the challenge of developing a custom tool in 48 hours based on votes for ideas provided by visitors to the show.

Silicon Impulse program adds partners to ease industrialisation of ultra-low power IC designs based on FD-SOI processes

Atrenta's SpyGlass line and others to be absorbed in Verification Continuum and Galaxy as part of EDA's latest major consolidation.

Docea Power has added a programming interface to the latest version of its Aceplorer power-modeling software to show how chipset designs would fare under a variety of software-based power-management algorithms.

RTL synthesis has joined the array of tools developed by Cadence Design Systems that employ distributed processing, with the aim of exploring more ways of creating area- and power-efficient logic blocks.

Mentor Graphics has released a programming interface to its Veloce emulators intended to support faster and more accurate power estimation.

Sonics is moving into power management with an approach intended to substantially automate much of the job of building finely grained power-gated SoCs.