DAC 2017

Sonics has developed a version of its power-management IP core for SoCs that adds support for dynamic voltage and frequency scaling, along with the ability to tune settings according to temperature.

Cliosoft sees a merging of social features and design-data repositories as driving more efficient reuse in chipmakers, bringing them together in its recently launched DesignHub product line.

Placement-aware synthesis and an array of post-layout recovery steps have helped drive up the clock speed and silicon utilization of a series high-end SoCs on leading-edge processes developed by customers of Synopsys' implementation tools.

An emulator that extends the reach of hardware acceleration into the world of multiphysics analysis could result from the merger of Siemens PLM Software with Mentor.

Former Cadence CEO tells DAC the IoT will lead to a burgeoning of chip design starts, followed by a brutal consolidation.

UltraSoc has donated to the RISC-V Foundation a specification for processor trace to try to provide the ecosystem with a common way of exporting runtime data to software tools.

At a DAC that will feature the arrival of the Accellera portable stimulus standard, Breker will demonstrate its implementation of the Early Adopter release of the specification.

Synopsys has released details on its varied activities at DAC 2017, ranging from panels to technical papers.

Mentor, a Siemens business, has released details on its varied activities at DAC 2017, ranging from panels to technical papers.

DAC's traditional training day is expanding into the field of machine learning this year in Austin.