Centaur opted for a superwide SIMD engine in an accelerator for a multicore x86 aimed at edge server applications that could take full advantage of spare die area.
The ESD Alliance is adding design and transportation-systems streams to the Semicon Europa 2019 show.
Do China's ambitions as a world-class innovator face fundamental challenges as a result of the sector's existing economic infrastructure?
DVCon USA is coming soon. Mentor's 2019 involvement includes a keynote from parent Siemens and a tutorial on managing your formal verification processes.
Cadence has added direct support for neural networks to the latest iteration of its DSP cores aimed at audio systems.
Cadence has launched an AI processor using an designed to take advantage of the sparse structure of typical deep neural networks.
For nVidia chief scientist and Stanford professor Bill Dally, now is a great time to be involved in hardware design, thanks to the rise of AI.
Cadence Design Systems’ Tensilica division has launched a variant of its Vision P6 processor core to tackle embedded designs that need to run a mixture of imaging and deep learning-type algorithms.
By the middle of this year Arm intends to deliver a processor designed specifically for deep-learning pipelines in edge devices, to capitalize on a move away from cloud computing for image and voice recognition.
Ceva has developed its first processor architecture aimed squarely at deep learning.
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