Cybersecurity must be built in not bolted on
Learn how one of the leading tool vendors addresses the security of its products and customer data through a ground-up cybersecurity strategy.
HLS
DAC 2021 Preview: Siemens EDA
DAC 2021 is looming and here is our first round up of a major EDA player's plans for the physical event in San Francisco.
Balancing PPA as machine learning moves to the edge
High-level synthesis is playing another important role in the matching of AI algorithms to necessarily application-specific designs.
Learn how Renesas uses SLEC to enhance its verification flows
A new technical article discusses Renesas' addition of SLEC to its SystemC and RTL flows and the improvements it achieved in time and coverage..
DVCon US 2020 preview: Mentor
Mentor will have a very broad presence at DVCon across technologies such as HLS, formal verification, simulation and emulation.
Master the design and verification of next gen transport: Part Three – functional safety
The third part of this series takes the original CNN demonstrator through a full ISO 26262 type functional safety workflow
Master the design and verification of next gen transport: Part Two – high-level synthesis
An object classification demonstrator shows how high-level synthesis (HLS) can speed the delivery and exploration of automotive design.
EDA with ‘AI inside’ – Mentor’s Joe Sawicki offers an insider’s view
Mentor has a host of tools - some public, some not - that leverage AI and ML. EVP Joe Sawicki has been describing the strategy behind their development.
Making the case for HLS in autonomous drive
The automotive market faces challenges that make it a prime candidate for the greater use of high-level synthesis on designs with AI and ML content.
C++ signoff made real
Konica Minolta describes how it has constructed a C++ signoff flow that mitigates code ambiguity, manual analysis and other inefficiencies.