A repeatable methodology for modern reset domain crossing issues
Reset domain crossing is another area where rising SoC complexity and IP reuse is causing an increase in reliability and safety challenges.
Author Archives: TDF Editor
C++ signoff made real
Konica Minolta describes how it has constructed a C++ signoff flow that mitigates code ambiguity, manual analysis and other inefficiencies.
The road to ES Design West: Design Pavilion
ES Design West aims to help integrate the supply chain but also has plenty of engineering content aimed at low power, security, embedded and more.
DVCon US and India chapters issue calls for submissions
The Bangalore conference has issued a last-minute call for panel proposals as technical paper submissions for the US edition get set to open next week.
How to automate pre-tape-out ESD protection verification
A new paper describes an alternative to increasingly inefficient manual ESD verification that reduces risks of respins and missed delivery deadlines.
The road to ES Design West: Location, location, location
There's still plenty of time to build a busy and profitable agenda for a visit to ES Design West and SEMICON West in San Francisco next week.
SmartDV adds verification IP for OpenCAPI data-center standard
The verification IP is the first to become commercially available for the bus interface backed by companies such as AMD, Google, IBM, Micron and Xilinx.
Verifying in an HLS context for AI and ML designs
A SystemC/C++ app from a library that extends the OneSpin 360 DV-Verify platform was used by ML IP specialist NanoSemi on a 5G/WiFi project.
The road to ES Design West: Cloud-based implementation
Moving design and verification activities into the cloud poses challenges. Next month's inaugural ES Design West will offer practical guidance.
Building an ecosystem around HLS for AI and ML designs
Mentor's AI Accelerator Ecosystem adds reference designs, libraries and other forms of support around its Catapult HLS platform.