code coverage


July 11, 2019

C++ signoff made real

Konica Minolta describes how it has constructed a C++ signoff flow that mitigates code ambiguity, manual analysis and other inefficiencies.
Article  |  Topics: Blog - EDA, - HLS, Verification  |  Tags: , , , ,   |  Organizations: ,
December 31, 2018

Closing code coverage with a hardware-aware HLS-to-RTL flow

Closing code coverage from HLS has been tricky because the C++ tools were built for software not hardware. But that is changing.
Article  |  Topics: Blog Topics  |  Tags: , , , , ,   |  Organizations:
October 17, 2018

FPGA playing verification catch-up as bugs escape

The latest Mentor-commissioned Wilson Research Group study on ASIC and FPGA verification highlights technique adoption and maturity.
Article  |  Topics: Verification  |  Tags: , , , , , ,   |  Organizations: ,

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