February 26, 2020
Tool development specialist Verific will demonstrate its parsers and their integration with INVIO APIs.
February 19, 2020
Six papers, a dedicated automotive sessions and demos including the use of the Nucleus for RISC-V are among highlights in Mentor's Embedded World agenda.
August 23, 2019
The automotive market faces challenges that make it a prime candidate for the greater use of high-level synthesis on designs with AI and ML content.
July 11, 2019
Konica Minolta describes how it has constructed a C++ signoff flow that mitigates code ambiguity, manual analysis and other inefficiencies.
July 2, 2019
A SystemC/C++ app from a library that extends the OneSpin 360 DV-Verify platform was used by ML IP specialist NanoSemi on a 5G/WiFi project.
June 27, 2019
Mentor's AI Accelerator Ecosystem adds reference designs, libraries and other forms of support around its Catapult HLS platform.
May 24, 2019
The company will highlight features within its Trek suite that comply with but then go beyond the capabilities of the Portable Stimulus Standard.
February 26, 2019
Tools that checks pre-synthesis C++ and SystemC code have historically had no understanding of hardware intent. The Catapult Design Checker fills that gap.
February 21, 2019
Verific Design Automation , specialist in parsers for SystemVerilog, VHDL and UPF, will also demo its INVIO platform with high level Python and C++ APIs.
December 31, 2018
Closing code coverage from HLS has been tricky because the C++ tools were built for software not hardware. But that is changing.