C

December 5, 2023

Zero ASIC open sources system simulation/emulation platform

Start-up launches platform on path to the specification, emulation and simulation of large chiplet-based designs.
December 3, 2021

DAC 2021 preview: Verific

Tool development enabler Verific will demonstrate its parsers, including a combination with the INVIO API platform at DAC 2021 in San Francisco next week.
Article  |  Topics: Conferences, Tool development, Verification  |  Tags: , , , , , , ,   |  Organizations: ,
February 26, 2020

DVCon US 2020 preview: Verific

Tool development specialist Verific will demonstrate its parsers and their integration with INVIO APIs.
Article  |  Topics: Blog Topics, Conferences, Blog - EDA, - Tool development, Verification  |  Tags: , , , , ,   |  Organizations: ,
February 19, 2020

Embedded World 2020 preview: Mentor

Six papers, a dedicated automotive sessions and demos including the use of the Nucleus for RISC-V are among highlights in Mentor's Embedded World agenda.
August 23, 2019

Making the case for HLS in autonomous drive

The automotive market faces challenges that make it a prime candidate for the greater use of high-level synthesis on designs with AI and ML content.
July 11, 2019

C++ signoff made real

Konica Minolta describes how it has constructed a C++ signoff flow that mitigates code ambiguity, manual analysis and other inefficiencies.
Article  |  Topics: Blog - EDA, - HLS, Verification  |  Tags: , , , ,   |  Organizations: ,
July 2, 2019

Verifying in an HLS context for AI and ML designs

A SystemC/C++ app from a library that extends the OneSpin 360 DV-Verify platform was used by ML IP specialist NanoSemi on a 5G/WiFi project.
June 27, 2019

Building an ecosystem around HLS for AI and ML designs

Mentor's AI Accelerator Ecosystem adds reference designs, libraries and other forms of support around its Catapult HLS platform.
May 24, 2019

DAC 2019 Preview: Breker Verification Systems

The company will highlight features within its Trek suite that comply with but then go beyond the capabilities of the Portable Stimulus Standard.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , , , , ,   |  Organizations: ,
February 26, 2019

A hardware-centric approach to checking HLS code before synthesis

Tools that checks pre-synthesis C++ and SystemC code have historically had no understanding of hardware intent. The Catapult Design Checker fills that gap.
Article  |  Topics: Blog Topics, HLS, RTL, Verification  |  Tags: , , , , ,   |  Organizations:

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