C


February 26, 2019

A hardware-centric approach to checking HLS code before synthesis

Tools that checks pre-synthesis C++ and SystemC code have historically had no understanding of hardware intent. The Catapult Design Checker fills that gap.
Article  |  Topics: Blog Topics, HLS, RTL, Verification  |  Tags: , , , , ,   |  Organizations:
February 21, 2019

DVCon USA 2019 preview: Verific Design Automation

Verific Design Automation , specialist in parsers for SystemVerilog, VHDL and UPF, will also demo its INVIO platform with high level Python and C++ APIs.
Article  |  Topics: Blog - EDA, - Tool development  |  Tags: , , , , , ,   |  Organizations: ,
December 31, 2018

Closing code coverage with a hardware-aware HLS-to-RTL flow

Closing code coverage from HLS has been tricky because the C++ tools were built for software not hardware. But that is changing.
Article  |  Topics: Blog Topics  |  Tags: , , , , ,   |  Organizations:
December 28, 2018

Why Mentor backs the PSS-DSL input format for the Portable Stimulus Specification

With PSS moving toward greater adoption, the Siemens vendor seems PSS-DSL as a winner in terms of conciseness and ease-of-adoption.
Article  |  Topics: Verification  |  Tags: , , , , , ,   |  Organizations: ,
December 7, 2017

Discover how ST adapted HLS for automotive imaging

ST has tweaked its standard HLS flow for ISPs to meet the requirements of ISO 26262
April 24, 2013

DAC 2013 Preview III: Embedded

DAC 2013 wants to bridge the gap between hardware and embedded software technical conferences, and has dedicated 35% of this year's technical program to that goal.
Article  |  Topics: Conferences, Blog - EDA, Embedded  |  Tags: , , , , , ,

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