Tools that checks pre-synthesis C++ and SystemC code have historically had no understanding of hardware intent. The Catapult Design Checker fills that gap.
Verific Design Automation , specialist in parsers for SystemVerilog, VHDL and UPF, will also demo its INVIO platform with high level Python and C++ APIs.
Closing code coverage from HLS has been tricky because the C++ tools were built for software not hardware. But that is changing.
With PSS moving toward greater adoption, the Siemens vendor seems PSS-DSL as a winner in terms of conciseness and ease-of-adoption.
ST has tweaked its standard HLS flow for ISPs to meet the requirements of ISO 26262
DAC 2013 wants to bridge the gap between hardware and embedded software technical conferences, and has dedicated 35% of this year's technical program to that goal.
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