Functional and safety verification specialist OneSpin Solutions has seen its 360 DV-Verify suite used on the development of machine learning (ML) IP for 5G and WiFi applications in a high-level synthesis (HLS) environment.
HLS is an increasingly popular abstraction level for a range of artificial intelligence (AI) and ML designs. It allows them to be developed at a higher level of abstraction, using SystemC and C++. This does not only shorten time-to-market but also eases AI and ML projects because they are typically based on algorithms realized in the same languages. However, achieving the most productive level co-design and co-verification can be challenging.
“Although designing in a high-level language has many advantages, it is critical that verification not be compromised,” says Raik Brinkmann, OneSpin’s president and chief executive officer. “The OneSpin solutions bring to SystemC/C++ verification groups the rich verification capabilities available for SystemVerilog and VHDL RTL designs.
OneSpin 360 DV-Verify at NanoSemi
OneSpin worked with NanoSemi on design for 5G and WiFi ML-based IP being made available for integration within an ASIC (the company also has products for test equipment and wireless infrastructure).
NanoSemi chose the OneSpin products because they support FPGA and SoC flows that dovetailed with its project. Its verification strategy used one of the apps available for the 360 DV-Verify platform (Figure 1) specifically addressing SystemC and C++. The app also has the benefit of not requiring user-built assertions.
Overall, 360 DV-Verify aims to provide a more automated unified, coverage-driven assertion-based verification flow that enables ‘what-if’ and other types of design exploration. As well as its SystemC/C++ app, OneSpin has apps that can be used on safety critical designs, particularly for markets such as automotive.
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