Real Intent has developed a tool to check design and the potential for circuits to glitch.
Real Intent has upgraded its Meridian CDC clock-domain crossing sign-off tool, with support for multimode-aware dynamic models.
A DVCon technical paper addresses potential reset domain crossing metastability issues due to UPF instrumentation.
Originally presented at DVCon Europe, a new paper automates complex steps in RDC verification and reduces noise.
Reset domain crossing is another area where rising SoC complexity and IP reuse is causing an increase in reliability and safety challenges.
A look at techniques to trap complex errors caused by signals crossing clock, reset and power domains is the focus of this upcoming webinar
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