Automating the pain out of clock domain crossing verification
A new CDC methodology uses automation and data hooks to improve a notoriously lengthy and tricky task - verifying synchronizers.
Author Archives: TDF Editor
Mentor delivers eMRAM test for ARM/Samsung FDSOI at 28nm
Tessent test suite targets automotive, AI and IoT projects that need embedded non-volatile memory.
Breker adds automated system integration test generation for RISC-V
App joins Portable Stimulus specialist's Trek5 family to reduce manual test writing during verification on designs for the fast-growing RISC-V open-source processor.
Master the design and verification of next gen transport: Part Four – emulation
Emulation is already playing a vital role in advanced automotive design within a digital twin environment.
Master the design and verification of next gen transport: Part Two – high-level synthesis
An object classification demonstrator shows how high-level synthesis (HLS) can speed the delivery and exploration of automotive design.
Master the design and verification of next gen transport: Part One – overview
What design solutions can best help deliver increasingly complex autonomous and ADAS systems?
How to achieve faster, more relevant early-stage DRC with Recon
The new Calibre Reconnaissance feature within Mentor's physical verification suite aims to maximize compute resources and deliver manageable reports.
Making the case for HLS in autonomous drive
The automotive market faces challenges that make it a prime candidate for the greater use of high-level synthesis on designs with AI and ML content.
Optimized DRC in the cloud
A new whitepaper describes some of the techniques you can use to get the most out of cloud-based DRC with Calibre.
Flash Memory Summit: Memblaze demos Toshiba ULL NVM technology
The Chinese memory module specialist will preview the 2020 launch of its new solution based on the ultra low latency XL-Flash technology from Toshiba.