Equivalence checking supports the efficient reuse of designs that reside on out-of-date silicon but remain valid in their own right.
The formal apps start-up has built strong positions in automotive and RISC-V and will strengthen Siemens in competition with Cadence.
DAC provided a forum for the growing number of verification efforts focused on checking the architectural compliance and overall RTL quality of RISC-V processors.
The verification specialist is adding more online resources to help engineers working from home during the Covid-19 pandemic.
A SystemC/C++ app from a library that extends the OneSpin 360 DV-Verify platform was used by ML IP specialist NanoSemi on a 5G/WiFi project.
OneSpin is bringing recent product launches to DAC and will have technical experts presenting within the conference's Designer Track.
The formal specialist is extending its line for Intel FPGAs that target areas such as AI/ML and HPC, and building out a RISC-V suite focused on ISA compliance.
Cadence and OneSpin are applying various forms of machine learning to their tools to automate formal verification.
The verification specialist will address the challenges posed by billion-gate SoCs and the integration of formal and simulation in its presentations.
OneSpin will focus at DVCon on its formal integrity verification platform for the RISC-V open-source which aims to speed up the core's adoption. The company will also feature the solution with a partner at EmbeddedWorld.
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