Siemens fuels custom IC flows with artificial intelligence
Three fast developing AI techniques underpin the efficiencies in the new Solido custom design and verification platform.
Author Archives: TDF Editor
Maximize manufacturing execution with HPC
Single-device tracking in the chiplet and multi-chip age needs a boost to deliver accuracy and greater production efficiency.
Alps Alpine composes capacitance IC with Symphony
The company says the mixed-signal platform enabled a 5X improvement in verification productivity.
Achieving functional coverage of multi-language designs
There is no comprehensive standard yet for functional coverage across designs using SystemC, TLM, UVM and SystemVerilog, but there are options using UVM Connect.
Siemens aims to simplify compliance for Linux medical devices
New Quality Package focuses on safety and cybersecurity compliance with EU and US medical device standards.
Chipletz pushes packaging design for AI, HPC and immersive use-cases
The Austin-based start-up used Siemens EDA software to deploy a cutting-edge Smart Substrate based on advanced packaging technology.
Arm adds Corellium expertise for IoT to its Virtual Hardware platform
The start-ups virtualization platform has already been gaining traction in comms and security.
Module verification demands integrated DRC and LVS
The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.
Use equivalence checking to retarget obsolete FPGA designs
Equivalence checking supports the efficient reuse of designs that reside on out-of-date silicon but remain valid in their own right.
Parasitic extraction challenges intensify for 5G
5G IC designs have needed aggressive innovation across many elements and more use of FD-SOI that both pose parasitic extraction challenges.