Three fast developing AI techniques underpin the efficiencies in the new Solido custom design and verification platform.
Author Archives: TDF Editor
Single-device tracking in the chiplet and multi-chip age needs a boost to deliver accuracy and greater production efficiency.
The company says the mixed-signal platform enabled a 5X improvement in verification productivity.
There is no comprehensive standard yet for functional coverage across designs using SystemC, TLM, UVM and SystemVerilog, but there are options using UVM Connect.
New Quality Package focuses on safety and cybersecurity compliance with EU and US medical device standards.
The Austin-based start-up used Siemens EDA software to deploy a cutting-edge Smart Substrate based on advanced packaging technology.
The start-ups virtualization platform has already been gaining traction in comms and security.
The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.
Equivalence checking supports the efficient reuse of designs that reside on out-of-date silicon but remain valid in their own right.
5G IC designs have needed aggressive innovation across many elements and more use of FD-SOI that both pose parasitic extraction challenges.