Author Archives: TDF Editor

The flat nature of traditional IC packaging design struggles to cope with the chiplet era. Homogeneous disaggregation offers an alternative.

The technique is becoming increasingly important for designs that need to be flexible, compact and lightweight.

DTCO (design technology co-optimization) looks to address systemic verification challenges but the process still needs to be extended.

Make it easier to capture issues in 2.5D and 3D designs with multiple chiplets and emerging challenges with this 'shift left' approach.

How the various features within today's Calibre physical verification family help designers shift left tasks and cut time-to-market.

A new paper looks at examples for using The Boundary Condition Independent Reduced Order Model (BCI-ROM) in its VHDL-AMS implementation for electro-thermal analysis.

EMA Design Automation to launch sister company, Accelerated Designs, to help clients streamline processes, cut manual effort, and connect data.

What are your options and what is one of the latest simulator features that helps streamline your build?

South Korea's leading research institute has built a reusable flow for lower power petaflops-performance AI.

Chiplet-based 3DIC designs present new challenges for flows that integrate tasks from design exploration to physical verification.