C++ signoff made real

By TDF Editor |  No Comments  |  Posted: July 11, 2019
Topics/Categories: Blog - EDA, - HLS, Verification  |  Tags: , , , ,  | Organizations: ,

Some companies began using high-level synthesis (HLS) for design well before its benefits became apparent for use-cases around AI and machine learning. For them, the next objective has been to use the same degree of abstraction to achieve C++ signoff.

C++ signoff offers potentially many benefits. In particular, simulation speeds are around one hundred times faster than those available at RTL. The problem is that most C++-focused methodologies so far have involved a large amount of manual checks and depended on the brute-force use of code coverage tools that are not hardware-aware, (chiefly GCOV). There has also been the risk of RTL-level mismatches due to undetected ambiguities that pass through the flow in the C++ code.

Konica Minolta was one of those early HLS adopters, applying it to products ranging across its peripherals, digital printing and healthcare product lines as well as projects for new markets. It has now constructed a C++ signoff methodology that overcomes many of the earlier limitations. It is based on the Catapult HLS and Questa simulation suites from Mentor, a Siemens business.

C++ signoff – before and after

The methodology and the use of the tools within it are described in a white paper. At its core, is the comparison between two methodologies, showing Konica’s earlier and updated design and verification flows.

The original flow underlines the amount of human review and brute-forcing required (Figure 1).

Figure 1. Original design and verification flow (Konica Minolta) - C++ signoff feature

Figure 1. Original design and verification flow (Konica Minolta)

Konica has now drawn upon a number of Catapult and Questa tools to build an alternative flow. The primary components are:

  • Catapult Design Checker: To employ static and formal techniques to find coding bugs and ambiguity in the C++ code.;
  • Catapult Coverage: To provide hardware-aware coverage analysis of the C++ code;
  • Assertion Synthesis: for the automatic generation of assertions in RTL code, based on C++assertions;
  • SCVerify: to automate the verification flow by leveraging the functional coverage of the C++testbench to provide a push-button smoke test; and
  • Questa Cover Check: to perform formal RTL coverage analysis to find unreachable code.

These have been assembled into the updated flow as shown in Figure 2.

Figure 2. Revised C++ signoff flow (Konica Minolta)

Figure 2. Revised C++ signoff flow (Konica Minolta)

Results and future plans

Having described the new flow, the paper goes on to describe the results Konica got when using it with regard to three of the most challenging areas:

  1. Checking C++ code
  2. Analyzing code coverage
  3. Finding unreachable code

As one example of its findings, the company say that it was able to detect 20 violations of an ‘Array Bound Read’ that reflected C++ code ambiguities which would have otherwise resulted in mismatches during RTL simulation.

Use of the tools is described in detail alongside further results from the new flow, and Konica says that it is now sufficiently confident in the enhanced C++ signoff flow that it aims to extend its use by LSI engineers, as shown in Figure 2, to algorithm developers also.

‘Konica Minolta proves C++ level signoff possibilities using Catapult HLS platform’ is available for download at this link.

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