electrostatic discharge


April 22, 2020

Analyzing common resistance to deliver design reliability

Automated resistance checks mitigate the increasing complexity involved when analyzing voltage drop, ESD and noise, particularly for analog-heavy designs.
July 3, 2019

How to automate pre-tape-out ESD protection verification

A new paper describes an alternative to increasingly inefficient manual ESD verification that reduces risks of respins and missed delivery deadlines.
Article  |  Topics: Design to Silicon, Blog - EDA, - Technical Articles, Verification  |  Tags: , ,   |  Organizations: ,

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