Tech Design Forum
Briefing
tape-out
tape-out
July 3, 2019
How to automate pre-tape-out ESD protection verification
A new paper describes an alternative to increasingly inefficient manual ESD verification that reduces risks of respins and missed delivery deadlines.
Article | Topics:
Design to Silicon
,
Blog - EDA
,
- Technical Articles
,
Verification
| Tags:
electrostatic discharge
,
ESD
,
tape-out
| Organizations:
Foundry
,
Siemens EDA
Briefing Topics
EDA
DFT
Electrical Design
Embedded
IP
PCB
Expert Insights
Tech Design Forum
EDA
EDA TOPICS
DFM
DFT
ESL
IC Implementation
Verification
MORE EDA
Expert Insights
Guides
EDA Home Page
IP
IP TOPICS
Assembly & Integration
Design Management
Selection
MORE IP
Expert Insights
Guides
IP Home Page
PCB
PCB TOPICS
Design Integrity
Layout & Routing
System Codesign
MORE PCB
Expert Insights
Guides
PCB Home Page
Embedded
EMBEDDED TOPICS
Architecture & Design
Integration & Debug
Platforms
User Experience
MORE EMBEDDED
Expert Insights
Guides
Embedded Home Page