EDA

A new whitepaper describes some of the techniques you can use to get the most out of cloud-based DRC with Calibre.

Safety verification calls for increased collaboration across the supply chain, experts say. The challenge is finding ways to make that happen.

Reset domain crossing is another area where rising SoC complexity and IP reuse is causing an increase in reliability and safety challenges.

Konica Minolta describes how it has constructed a C++ signoff flow that mitigates code ambiguity, manual analysis and other inefficiencies.

Coventor has updated its SEMulator virtual-fab tool and added the ability to tune process windows based on simulation results.

ES Design West aims to help integrate the supply chain but also has plenty of engineering content aimed at low power, security, embedded and more.

A new paper describes an alternative to increasingly inefficient manual ESD verification that reduces risks of respins and missed delivery deadlines.

There's still plenty of time to build a busy and profitable agenda for a visit to ES Design West and SEMICON West in San Francisco next week.

The verification IP is the first to become commercially available for the bus interface backed by companies such as AMD, Google, IBM, Micron and Xilinx.

A SystemC/C++ app from a library that extends the OneSpin 360 DV-Verify platform was used by ML IP specialist NanoSemi on a 5G/WiFi project.