Coventor


May 9, 2018

Motion harvester wins MEMS design contest

Energy harvesting, mechanical reprogrammable logic, and genetic algorithms were among the finalists for the MEMS design competition.
June 10, 2016

RC extraction from ‘virtual fab’ models may speed PDK availability

Electrical analysis facility does RC extraction on virtual fab models, accelerating the availability of early PDKs for new processes
Article  |  Topics: Conferences, Blog - EDA  |  Tags: , ,   |  Organizations:
March 16, 2016

MEMS contest launches at DATE

The DATE 2016 conference saw the launch of a competition to encourage novel designs using MEMS technology.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations: , ,
February 23, 2016

Directed self assembly may offer similar benefits to EUV, process modeling study says

Directed self assembly techniques may offer similar benefits to EUV lithography, especially for DRAM makers, says SPIE conference paper
Article  |  Topics: Conferences  |  Tags: , , , ,   |  Organizations:
December 7, 2015

Asymmetric variability issues could impact 7nm processes

Simulation shows 7nm process will need tighter variability control than expected, and possibly accommodation for asymmetric variability
Article  |  Topics: Conferences, Design to Silicon  |  Tags: , , ,   |  Organizations: , ,
October 28, 2014

imec and Coventor partner for 7nm process development

Process development alliance will enable Imec to experiment on 10 and 7nm processes in the computer before moving to the fab
Article  |  Topics: Design to Silicon  |  Tags: , , , ,   |  Organizations: ,
May 28, 2013

Fabless, IP designers need process simulation tools, says Coventor CTO

Fabless designers and IP providers need process simulation tools to understand how process variability could affect their designs.
Article  |  Topics: Design to Silicon, Blog - IP  |  Tags: , , ,   |  Organizations:
December 12, 2012

Process development needs hierarchy, abstraction, says tools CTO

How to save money in process development by moving experiments out of the fab and into the computer.
Article  |  Topics: Design to Silicon  |  Tags: , , ,   |  Organizations:
December 4, 2012

FinFET tipsheet for IEDM

finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?

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