Just how much of the flow has already has 'shift left' benefit and what is fueling further progress.
Calibre Design Enhancer moves physical verification checks and automated DRC-clean via and cell insertion into P&R
Single-device tracking in the chiplet and multi-chip age needs a boost to deliver accuracy and greater production efficiency.
Advanced packaging requirements from foundries and OSATs pose stringent challenges. A new paper describes three ways of satisfying them.
DAC 2021 is looming and here is our first round up of a major EDA player's plans for the physical event in San Francisco.
Learn how Calibre RealTime Digital allows you to identify, explore and fix DRC violations as you go.
A case study describes how the RF and AMS specialist achieved efficiencies on a complex server DSP SoC project by running as-you-go DRC during place and route.
Live and on-demand videos as well as You Tube 'tips and techniques' clips form part of a wide 'work at home' support package from Mentor.
By analyzing topology during the schematic design phase, you can detect latch-up issues before post-layout ERCs and avoid late stage revisions.
Mentor has a host of tools - some public, some not - that leverage AI and ML. EVP Joe Sawicki has been describing the strategy behind their development.
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