DAC 2021 Preview: Siemens EDA
DAC 2021 is looming and here is our first round up of a major EDA player's plans for the physical event in San Francisco.
DFM
From iterative to in-design DRC and debug for place and route
Learn how Calibre RealTime Digital allows you to identify, explore and fix DRC violations as you go.
How MaxLinear cut physical verification time with in-design DRC
A case study describes how the RF and AMS specialist achieved efficiencies on a complex server DSP SoC project by running as-you-go DRC during place and route.
Coronavirus Resources: Mentor
Live and on-demand videos as well as You Tube 'tips and techniques' clips form part of a wide 'work at home' support package from Mentor.
Earlier latch-up prevention with topology-based analysis
By analyzing topology during the schematic design phase, you can detect latch-up issues before post-layout ERCs and avoid late stage revisions.
EDA with ‘AI inside’ – Mentor’s Joe Sawicki offers an insider’s view
Mentor has a host of tools - some public, some not - that leverage AI and ML. EVP Joe Sawicki has been describing the strategy behind their development.
Optimized DRC in the cloud
A new whitepaper describes some of the techniques you can use to get the most out of cloud-based DRC with Calibre.
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