Coventor has released version 8.0 of its SEMulator3D tool for simulating complete semiconductor process flows, including a module designed to help tune process windows for yield and device performance without needing a series of physical wafer runs.
In addition to the process window optimization functions, SEMulator3D 8.0 adds electrical analysis and improvements to the transistor modeling behavior. This includes small-signal AC analysis to extract device capacitance and use the results to explore transistor process variability on device performance. A new variety of physical phenomena, such as field-dependent recombination and band-to-band tunneling, are now supported in the device solver.
In the electrical analysis module, a ‘Validate Netlist’ function is now available to check extracted netlists against references supplied using circuit design language (CDL) descriptions by third-party EDA tools. Coventor has also sped up the resistance and capacitance solvers by as much as forty-fold in some cases compared to the previous version of the tool.
To support site-specific flows, version 8.0 adds a feature to import custom process flows and create SEMulator3D input files. And a new Monte Carlo implant step provides a more realistic ion implantation model.