DRC

July 20, 2020

Mentor tunes LVS for early SoC integration

Mentor has released a tool that attempts to deal with the problems encountered in the use of physical circuit verification in the early stages of SoC integration.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
June 15, 2020

EDA in the cloud boosts DRC iterations for AMD

AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.
Article  |  Topics: Blog Topics  |  Tags: , , , , , , , , ,   |  Organizations: , , ,
December 18, 2019

On-demand DRC within P&R cuts closure time in half for MaxLinear

Case study describes how RF/AMS specialist used Calibre RealTime Digital within its flow for a high-end DSP SoC.
August 27, 2019

How to achieve faster, more relevant early-stage DRC with Recon

The new Calibre Reconnaissance feature within Mentor's physical verification suite aims to maximize compute resources and deliver manageable reports.
Article  |  Topics: Digital/analog implementation, Verification  |  Tags: , , , , , , , ,   |  Organizations:
August 15, 2019

Optimized DRC in the cloud

A new whitepaper describes some of the techniques you can use to get the most out of cloud-based DRC with Calibre.
January 21, 2019

Video series details the physical verification process

Physical verification challenge of large SoCs on leading-edge processes detailed in video series
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , ,   |  Organizations:
November 14, 2018

Case study: Achieving earlier signoff convergence and a ‘shift left’ for P&R at Qualcomm

Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.
Article  |  Topics: Blog - EDA, - GDSII, Verification  |  Tags: , , , , , , ,   |  Organizations: ,
June 19, 2018

Mentor targets DRC efficiencies for place-and-route with Calibre RealTime Digital

Early users of the new P&R integrated physical verification tool say time-to-sign-off was cut by 40% and above.
Article  |  Topics: Verification  |  Tags: , , , , ,   |  Organizations:
April 12, 2017

Cadence cuts up DRC for speed

Cadence Design Systems has launched a design-rule checking engine that can distribute its workload across multiple servers in a cloud, private farm or mixture of both to speed up signoff.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
January 17, 2017

DesignCon 2017 preview: Mentor Graphics

DesignCon 2017 takes place from Jan 31 to Feb 2 at the Santa Clara Convention Center with its usual focus on PCB design and implementation.

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