Physical verification challenge of large SoCs on leading-edge processes detailed in video series
Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.
Early users of the new P&R integrated physical verification tool say time-to-sign-off was cut by 40% and above.
Cadence Design Systems has launched a design-rule checking engine that can distribute its workload across multiple servers in a cloud, private farm or mixture of both to speed up signoff.
DesignCon 2017 takes place from Jan 31 to Feb 2 at the Santa Clara Convention Center with its usual focus on PCB design and implementation.
Flow draws on existing strengths in Xpedition, Valor, Nimbic and Flotherm among others to optimize 3D design projects and improve cross-disciplinary communication.
The Silicon Integration Initiative (Si2) is targeting the end of the year for release 2.0 of its OpenDFM standard, which will include support for DRC+ and make it possible to build search engines for yield.
But as it celebrates a decade of OpenAccess, the standards body also looks toward the future in PDKs, advanced DFM and 3D.
SpringSoft is trying a different approach to constraint-based design in a bid to improve the automation of custom and mixed-signal design, particularly on advanced process nodes.
Can pattern recognition improve deign rule checking at advanced nodes?
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