Mentor has released a tool that attempts to deal with the problems encountered in the use of physical circuit verification in the early stages of SoC integration.
AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.
Case study describes how RF/AMS specialist used Calibre RealTime Digital within its flow for a high-end DSP SoC.
The new Calibre Reconnaissance feature within Mentor's physical verification suite aims to maximize compute resources and deliver manageable reports.
A new whitepaper describes some of the techniques you can use to get the most out of cloud-based DRC with Calibre.
Physical verification challenge of large SoCs on leading-edge processes detailed in video series
Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.
Early users of the new P&R integrated physical verification tool say time-to-sign-off was cut by 40% and above.
Cadence Design Systems has launched a design-rule checking engine that can distribute its workload across multiple servers in a cloud, private farm or mixture of both to speed up signoff.
DesignCon 2017 takes place from Jan 31 to Feb 2 at the Santa Clara Convention Center with its usual focus on PCB design and implementation.
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