DRC

April 11, 2024

Refining DTCO to bridge data walls in system design

DTCO (design technology co-optimization) looks to address systemic verification challenges but the process still needs to be extended.
July 10, 2023

Calibre ‘shifts left’ into place and route

Calibre Design Enhancer moves physical verification checks and automated DRC-clean via and cell insertion into P&R
Article  |  Topics: DFM, Digital/analog implementation, Blog - EDA, - Verification  |  Tags: , , ,   |  Organizations: ,
September 8, 2022

Module verification demands integrated DRC and LVS

The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.
July 13, 2022

Siemens pushes DRC to the left

Siemens has launched Calibre DRC engines that make it easier to perform useful checks early in the layout process.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
July 11, 2022

Fujimura asks EDA to bend towards manufacturability

Aki Fujimura of mask specialist D2S sees curved shapes as key to improving die yield and performance but it needs EDA support.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , , ,   |  Organizations: ,
June 16, 2022

TSMC certifies Aprisa for N5 and N4

TSMC has certified the Aprisa place-and-route software from Siemens Digital Industries Software for the N5 and N4 process technologies.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
July 28, 2021

Automate latchup verification for 3DIC

A Siemens white paper describes a way of automatically deriving information from 2.5D/3DIC designs to streamline latchup design-rules verification.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
May 14, 2021

How MaxLinear cut physical verification time with in-design DRC

A case study describes how the RF and AMS specialist achieved efficiencies on a complex server DSP SoC project by running as-you-go DRC during place and route.
July 20, 2020

Mentor tunes LVS for early SoC integration

Mentor has released a tool that attempts to deal with the problems encountered in the use of physical circuit verification in the early stages of SoC integration.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
June 15, 2020

EDA in the cloud boosts DRC iterations for AMD

AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.
Article  |  Topics: Blog Topics  |  Tags: , , , , , , , , ,   |  Organizations: , , ,

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