How to achieve faster, more relevant early-stage DRC with Recon
The new Calibre Reconnaissance feature within Mentor's physical verification suite aims to maximize compute resources and deliver manageable reports.
Archives
Making the case for HLS in autonomous drive
The automotive market faces challenges that make it a prime candidate for the greater use of high-level synthesis on designs with AI and ML content.
Flash Memory Summit: Memblaze demos Toshiba ULL NVM technology
The Chinese memory module specialist will preview the 2020 launch of its new solution based on the ultra low latency XL-Flash technology from Toshiba.
Accellera sets up public code repository
Accellera has set up a public repository for the source code and other supplemental material needed for its standards.
Arm opts for more flexibility in licensing
Arm has introduced a licensing model that makes it easier to try out cores during a design before committing to production.
Coventor updates process simulation tool
Coventor has updated its SEMulator virtual-fab tool and added the ability to tune process windows based on simulation results.
The road to ES Design West: Design Pavilion
ES Design West aims to help integrate the supply chain but also has plenty of engineering content aimed at low power, security, embedded and more.
How to automate pre-tape-out ESD protection verification
A new paper describes an alternative to increasingly inefficient manual ESD verification that reduces risks of respins and missed delivery deadlines.
The road to ES Design West: Location, location, location
There's still plenty of time to build a busy and profitable agenda for a visit to ES Design West and SEMICON West in San Francisco next week.
SmartDV adds verification IP for OpenCAPI data-center standard
The verification IP is the first to become commercially available for the bus interface backed by companies such as AMD, Google, IBM, Micron and Xilinx.