How to achieve faster, more relevant early-stage DRC with Recon

By TDF Editor |  No Comments  |  Posted: August 27, 2019
Topics/Categories: Digital/analog implementation, Verification  |  Tags: , , , , , , , ,  | Organizations:

Design teams increasingly need to run chip integration and block development in parallel. Shortening deadlines is one factor, increasing complexity is another and alongside them there is the desire to undertake earlier design exploration and verification. The sooner you can catch errors like, say, routing violations, the more time and money you save.

But trying to undertake chip-level physical verification relatively soon has risks. Early-stage DRC can throw up, for example, a massive number of floorplanning violations, but given the relative immaturity of the project, not all of them will necessarily be ‘real’. And each one of these runs will itself take a long time to complete, likely generating a massive database in the process.

Calibre Reconnaissance (Recon)

One of the latest addition to Mentor’s Calibre physical verification suite is Calibre Reconnaissance (Recon). Its purpose is to make early stage DRC more manageable in terms of resources and times and more relevant in terms of the results it produces.

Compatible with all foundry and IDM processes, Recon has three main features.

Automatic check selection

Deselecting some rules from the deck can greatly reduce early stage DRC runs, but you need to know which ones to pick. Choosing them manually can take up a lot of time in itself. Calibre Recon takes into account the development phase and automatically deselects typically 50% of checks, depending on the target node as well as the design’s maturity. Recon can here typically reduce the number of reported violations by 70%. User-designated checks are also honored within these runs.

Gray box exclusion

For early-stage DRC, it is likely that some blocks will still be so immature in their development that DRC runs across them would be either misleading or pointless. Recon allows users to tell the run to ignore these areas concentrating on, say, top-level routing but ignoring cell details. The pruning of a design like this can introduce errors in itself, but these can be avoided by using Recon in conjunction with the Calibre Auto-Waivers function to exclude those reports.

DRC Analyze

This feature allows users to visualize results as histograms or colormaps, so that users can drill down to identify errors for further review or debug on on opportunistic basis.

A recently-published technical article takes a deeper dive into how Recon helps to enable meaningful DRC while a project is still evolving. ‘Accelerate early design exploration and verification for faster time-to-market’ is available at this link.

 

Leave a Comment

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors