‘Shocking’ quality sees vendors organize around RISC-V verification
Three EDA vendors team up to create stronger verification flow for RISC-V processor implementations.
hardware-software co-design
Balancing PPA as machine learning moves to the edge
High-level synthesis is playing another important role in the matching of AI algorithms to necessarily application-specific designs.
Cadence to acquire AWR from National Instruments
Cadence Design Systems has agreed to buy the AWR RF-design company from its current owner National Instruments for approximately $160m.
Making the case for HLS in autonomous drive
The automotive market faces challenges that make it a prime candidate for the greater use of high-level synthesis on designs with AI and ML content.
SNUG 2016: Aart de Geus looks beyond the linear design flow
Do the synapses in the human brain offer a new model for the design flow in a Smart Everything world?
Carbon introduces exchange for building and stressing virtual prototypes
Carbon Design Systems has introduced a web portal to streamline the process of finding the most appropriate executable models for a system-level virtual prototype.
Cadence brings FPGA prototyping and emulation into sync
Cadence Design Systems has developed an FPGA-based prototyping system that takes advantage of much closer alignment with its existing Palladium XP emulator to accelerate bring-up and support debugging across both platforms.
Verification perspectives: the growth of emulation
The first in a series of articles on how various vendors are addressing the flow's most challenging task looks at Mentor's strategy for emulation.
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