A new technical article discusses Renesas' addition of SLEC to its SystemC and RTL flows and the improvements it achieved in time and coverage..
October's DVCon Europe conference will have an increased focus on the role of software in electronic systems and the challenges it poses to verification.
The automotive market faces challenges that make it a prime candidate for the greater use of high-level synthesis on designs with AI and ML content.
Accellera has set up a public repository for the source code and other supplemental material needed for its standards.
Tools that checks pre-synthesis C++ and SystemC code have historically had no understanding of hardware intent. The Catapult Design Checker fills that gap.
Closing code coverage from HLS has been tricky because the C++ tools were built for software not hardware. But that is changing.
Accellera has published version 1.0 of the SystemC Configuration, Control and Inspection (CCI) standard.
Accellera has released a maintenance update to the SystemC core language library that addresses a number of issues that users have reported over the past three years.
The massive complexity of 5G and automotive systems and the need for advanced verification techniques set the scene for DVCon Europe this year.
DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.
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