systemc

November 3, 2021

Python provides the link for speed checks at Sondrel

Sondrel has combined EDA tools with custom SystemC and Python code to develop a system that can help automate the detailed performance analysis of high-level architectures before RTL is generated.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations: ,
October 13, 2021

DVCon events stick with virtual format and add speakers

DVCon US use a virtual platform for its event to be held in the spring and the organisers of the European event will employ a more sophisticated version of the virtual 3D space debuted last year.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
February 28, 2020

Learn how Renesas uses SLEC to enhance its verification flows

A new technical article discusses Renesas' addition of SLEC to its SystemC and RTL flows and the improvements it achieved in time and coverage..
Article  |  Topics: Blog - EDA, - HLS  |  Tags: , , ,   |  Organizations: ,
October 14, 2019

DVCon Europe looks to software for next phase in verification

October's DVCon Europe conference will have an increased focus on the role of software in electronic systems and the challenges it poses to verification.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
August 23, 2019

Making the case for HLS in autonomous drive

The automotive market faces challenges that make it a prime candidate for the greater use of high-level synthesis on designs with AI and ML content.
July 31, 2019

Accellera sets up public code repository

Accellera has set up a public repository for the source code and other supplemental material needed for its standards.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
February 26, 2019

A hardware-centric approach to checking HLS code before synthesis

Tools that checks pre-synthesis C++ and SystemC code have historically had no understanding of hardware intent. The Catapult Design Checker fills that gap.
Article  |  Topics: Blog Topics, HLS, RTL, Verification  |  Tags: , , , , ,   |  Organizations:
December 31, 2018

Closing code coverage with a hardware-aware HLS-to-RTL flow

Closing code coverage from HLS has been tricky because the C++ tools were built for software not hardware. But that is changing.
Article  |  Topics: Blog Topics  |  Tags: , , , , ,   |  Organizations:
June 14, 2018

Accellera signs off on SystemC control standard

Accellera has published version 1.0 of the SystemC Configuration, Control and Inspection (CCI) standard.
Article  |  Topics: Blog - EDA, IP  |  Tags: ,   |  Organizations:
October 16, 2017

Accellera updates SystemC library

Accellera has released a maintenance update to the SystemC core language library that addresses a number of issues that users have reported over the past three years.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: ,   |  Organizations:

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