There is no comprehensive standard yet for functional coverage across designs using SystemC, TLM, UVM and SystemVerilog, but there are options using UVM Connect.
Sondrel has combined EDA tools with custom SystemC and Python code to develop a system that can help automate the detailed performance analysis of high-level architectures before RTL is generated.
DVCon US use a virtual platform for its event to be held in the spring and the organisers of the European event will employ a more sophisticated version of the virtual 3D space debuted last year.
A new technical article discusses Renesas' addition of SLEC to its SystemC and RTL flows and the improvements it achieved in time and coverage..
October's DVCon Europe conference will have an increased focus on the role of software in electronic systems and the challenges it poses to verification.
The automotive market faces challenges that make it a prime candidate for the greater use of high-level synthesis on designs with AI and ML content.
Accellera has set up a public repository for the source code and other supplemental material needed for its standards.
Tools that checks pre-synthesis C++ and SystemC code have historically had no understanding of hardware intent. The Catapult Design Checker fills that gap.
Closing code coverage from HLS has been tricky because the C++ tools were built for software not hardware. But that is changing.
Accellera has published version 1.0 of the SystemC Configuration, Control and Inspection (CCI) standard.
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