November 3, 2021
Sondrel has combined EDA tools with custom SystemC and Python code to develop a system that can help automate the detailed performance analysis of high-level architectures before RTL is generated.
October 13, 2021
DVCon US use a virtual platform for its event to be held in the spring and the organisers of the European event will employ a more sophisticated version of the virtual 3D space debuted last year.
February 28, 2020
A new technical article discusses Renesas' addition of SLEC to its SystemC and RTL flows and the improvements it achieved in time and coverage..
October 14, 2019
October's DVCon Europe conference will have an increased focus on the role of software in electronic systems and the challenges it poses to verification.
August 23, 2019
The automotive market faces challenges that make it a prime candidate for the greater use of high-level synthesis on designs with AI and ML content.
July 31, 2019
Accellera has set up a public repository for the source code and other supplemental material needed for its standards.
February 26, 2019
Tools that checks pre-synthesis C++ and SystemC code have historically had no understanding of hardware intent. The Catapult Design Checker fills that gap.
December 31, 2018
Closing code coverage from HLS has been tricky because the C++ tools were built for software not hardware. But that is changing.
June 14, 2018
Accellera has published version 1.0 of the SystemC Configuration, Control and Inspection (CCI) standard.
October 16, 2017
Accellera has released a maintenance update to the SystemC core language library that addresses a number of issues that users have reported over the past three years.
