systemc

July 31, 2019

Accellera sets up public code repository

Accellera has set up a public repository for the source code and other supplemental material needed for its standards.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
February 26, 2019

A hardware-centric approach to checking HLS code before synthesis

Tools that checks pre-synthesis C++ and SystemC code have historically had no understanding of hardware intent. The Catapult Design Checker fills that gap.
Article  |  Topics: Blog Topics, HLS, RTL, Verification  |  Tags: , , , , ,   |  Organizations:
December 31, 2018

Closing code coverage with a hardware-aware HLS-to-RTL flow

Closing code coverage from HLS has been tricky because the C++ tools were built for software not hardware. But that is changing.
Article  |  Topics: Blog Topics  |  Tags: , , , , ,   |  Organizations:
June 14, 2018

Accellera signs off on SystemC control standard

Accellera has published version 1.0 of the SystemC Configuration, Control and Inspection (CCI) standard.
Article  |  Topics: Blog - EDA, IP  |  Tags: ,   |  Organizations:
October 16, 2017

Accellera updates SystemC library

Accellera has released a maintenance update to the SystemC core language library that addresses a number of issues that users have reported over the past three years.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: ,   |  Organizations:
September 22, 2017

5G and automotive provide applications focus for DVCon Europe

The massive complexity of 5G and automotive systems and the need for advanced verification techniques set the scene for DVCon Europe this year.
May 2, 2017

Wally Rhines looks beyond ‘endless verification’ to the system era

DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.
February 15, 2017

DVCon US 2017 preview: Mentor Graphics

The major verification conference is looming and Mentor's participation will include tutorials that explore the latest in portable stimulus, SystemC, VIP and more.
September 13, 2016

DVCon Europe to examine role of UVM, SystemC in system-level verification

DVCon Europe this year provides a venue for extending UVM, SystemC and TLM for faster, more effective verification its organizing committee claims.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations:
August 15, 2016

SystemC materials move to Apache 2.0 license

Accellera has moved to an Apache 2.0 open-source license for all of the supplementary materials for its SystemC library.
Article  |  Topics: Blog - EDA, IP  |  Tags: ,   |  Organizations:

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