December 10, 2019
App joins Portable Stimulus specialist's Trek5 family to reduce manual test writing during verification on designs for the fast-growing RISC-V open-source processor.
August 27, 2019
The new Calibre Reconnaissance feature within Mentor's physical verification suite aims to maximize compute resources and deliver manageable reports.
May 28, 2019
The company is also bundling its new CPU and GPU cores in a premium IP platform that can be tuned for next generation applications and devices.
June 8, 2017
Vendor concentrates on memory IP products at 2017 Design Automation Conference.
October 14, 2016
Catch up with the vendor's plans for the ARM technical conference in Santa Clara later this month.
December 10, 2015
Cortus has added to its version 2 architecture a processor core that offers hardware support for floating-point code.
March 24, 2015
Flow draws on existing strengths in Xpedition, Valor, Nimbic and Flotherm among others to optimize 3D design projects and improve cross-disciplinary communication.
October 7, 2014
Minimal IP cores are meant to serve broader market than IoT, using revised instruction set to increase code density, save on chip memory and enable security
June 6, 2014
Online portals enable ASIC designers to explore IP and delivery options, enabling lower-cost markets such as IoT
December 16, 2013
Synopsys launches HAPS-DX, an FPGA-based IP and subsystem prototyping system, with an optimized toolchain and interoperability with HAPS-70 systems.