App joins Portable Stimulus specialist's Trek5 family to reduce manual test writing during verification on designs for the fast-growing RISC-V open-source processor.
The new Calibre Reconnaissance feature within Mentor's physical verification suite aims to maximize compute resources and deliver manageable reports.
The company is also bundling its new CPU and GPU cores in a premium IP platform that can be tuned for next generation applications and devices.
Vendor concentrates on memory IP products at 2017 Design Automation Conference.
Catch up with the vendor's plans for the ARM technical conference in Santa Clara later this month.
Cortus has added to its version 2 architecture a processor core that offers hardware support for floating-point code.
Flow draws on existing strengths in Xpedition, Valor, Nimbic and Flotherm among others to optimize 3D design projects and improve cross-disciplinary communication.
Minimal IP cores are meant to serve broader market than IoT, using revised instruction set to increase code density, save on chip memory and enable security
Online portals enable ASIC designers to explore IP and delivery options, enabling lower-cost markets such as IoT
Synopsys launches HAPS-DX, an FPGA-based IP and subsystem prototyping system, with an optimized toolchain and interoperability with HAPS-70 systems.
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