routing


August 27, 2019

How to achieve faster, more relevant early-stage DRC with Recon

The new Calibre Reconnaissance feature within Mentor's physical verification suite aims to maximize compute resources and deliver manageable reports.
Article  |  Topics: Digital/analog implementation, Verification  |  Tags: , , , , , , , ,   |  Organizations:
May 24, 2015

Cadence updates Allegro with PCB production and routing tools

Cadence has launched the 16.6 release of its Allegro PCB-design portfolio, adding modules for manufacturing documentation and design-rule preparation aids.
Article  |  Topics: Blog - PCB  |  Tags: , , , , ,   |  Organizations:
January 5, 2015

Cadence high-level synthesis changes deal with congestion

SystemC coding style can lead to excessive congestion in the logic generated by high-level synthesis. Cadence described how it is attacking the issue at its recent Front-End Design Summit.
November 24, 2014

A57 finFET design underlines routing challenges

In a presentation at the recent ARM TechCon, HiSilicon described the issues in putting together a 16nm finFET-based design built around a cluster of ARM’s Cortex A57 processors.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: ,
March 17, 2014

Mentor begins to take wraps off Xpedition PCB software overhaul

New-look Xpedition flow launches with preview of layout features including better control over automation, 2D/3D views, and a UI even for 'casual' users.
Article  |  Topics: Blog Topics, Blog - PCB, - Product  |  Tags: , , , ,   |  Organizations:
July 9, 2013

Xilinx tapes out for first of 20nm-generation FPGAs

Xilinx aims to be first of the FPGA makers to produce 20nm devices, expecting to move to production samples for some products by the end of the year.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , , , ,   |  Organizations:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors