Shift left: what it does and how to make it happen
Get to know more on the specific benefits of shift left and how to achieve easy adoption.
routing
Fujimura asks EDA to bend towards manufacturability
Aki Fujimura of mask specialist D2S sees curved shapes as key to improving die yield and performance but it needs EDA support.
How to achieve faster, more relevant early-stage DRC with Recon
The new Calibre Reconnaissance feature within Mentor's physical verification suite aims to maximize compute resources and deliver manageable reports.
Cadence updates Allegro with PCB production and routing tools
Cadence has launched the 16.6 release of its Allegro PCB-design portfolio, adding modules for manufacturing documentation and design-rule preparation aids.
Cadence high-level synthesis changes deal with congestion
SystemC coding style can lead to excessive congestion in the logic generated by high-level synthesis. Cadence described how it is attacking the issue at its recent Front-End Design Summit.
A57 finFET design underlines routing challenges
In a presentation at the recent ARM TechCon, HiSilicon described the issues in putting together a 16nm finFET-based design built around a cluster of ARM’s Cortex A57 processors.
Mentor begins to take wraps off Xpedition PCB software overhaul
New-look Xpedition flow launches with preview of layout features including better control over automation, 2D/3D views, and a UI even for 'casual' users.
Xilinx tapes out for first of 20nm-generation FPGAs
Xilinx aims to be first of the FPGA makers to produce 20nm devices, expecting to move to production samples for some products by the end of the year.
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