July 11, 2022
Aki Fujimura of mask specialist D2S sees curved shapes as key to improving die yield and performance but it needs EDA support.
August 27, 2019
The new Calibre Reconnaissance feature within Mentor's physical verification suite aims to maximize compute resources and deliver manageable reports.
May 24, 2015
Cadence has launched the 16.6 release of its Allegro PCB-design portfolio, adding modules for manufacturing documentation and design-rule preparation aids.
January 5, 2015
SystemC coding style can lead to excessive congestion in the logic generated by high-level synthesis. Cadence described how it is attacking the issue at its recent Front-End Design Summit.
November 24, 2014
In a presentation at the recent ARM TechCon, HiSilicon described the issues in putting together a 16nm finFET-based design built around a cluster of ARM’s Cortex A57 processors.
March 17, 2014
New-look Xpedition flow launches with preview of layout features including better control over automation, 2D/3D views, and a UI even for 'casual' users.
July 9, 2013
Xilinx aims to be first of the FPGA makers to produce 20nm devices, expecting to move to production samples for some products by the end of the year.